National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ User Manual
Page 207
Index
© National Instruments Corporation
Index-11
Lab-PC+ User Manual
N
NI-DAQ driver software, 1-2 to 1-3
NRSE input (eight channels)
configuration, 2-13
definition (table), 2-11
signal connection considerations
recommended configurations (table), 3-6
single-ended connections, 3-11 to 3-12
O
OBF* signal
description, 3-17
Mode 1 output timing, 3-19
Mode 2 bidirectional timing, 3-20
Port C signal assignments (table), 3-16
OBFA* status word, Port C
Mode 1 output, E-30
Mode 2 operation, E-32
OBFB* status word, Port C, E-30
OKI 82C53 data sheet, B-1 to B-13
OKI 82C55A data sheet, C-1 to C-23
operation of Lab-PC+. See theory of
operation.
OUT signal. See GATE, CLK, and OUT
signals.
OUTA1 signal, controlled acquisition
mode, E-12
OUTA2 signal, interrupt
programming, E-22 to E-23
OUTB0 signal (table), 3-3
OUTB1 signal, interval scanning, E-18
OUTB2 signal (table), 3-3
OVERFLOW bit
A/D FIFO overflow condition
analog input circuitry programming, E-4
controlled acquisition programming, E-8
posttrigger mode, E-14
pretrigger mode, E-16
freerun acquisition programming, E-10
A/D interrupt programming, E-20
description, D-7
OVERRUN bit
A/D FIFO overrun condition
clearing the analog input circuitry, E-5
controlled acquisition programming, E-8
posttrigger mode, E-14
pretrigger mode, E-16
freerun acquisition programming, E-10
A/D interrupt programming, E-20
description, D-8
P
PAO<0..7> signal (table), 3-3
PBO<0..7> signal (table), 3-3
PC bus interface, 2-1
factory settings (table), 2-3
PC I/O channel interface circuitry
block diagram, 4-3
theory of operation, 4-2 to 4-4
PCO<0..7> signal (table), 3-3
physical specifications, A-6
polarity configuration
analog input
bipolar, 2-13 to 2-14
unipolar, 2-14
analog output
bipolar, 2-9
unipolar, 2-10
Port A Register, D-34
Port B Register, D-35
Port C Register
description, D-36
pin assignments
Mode 1 input, E-28
Mode 1 output, E-30
Mode 2 operation, E-33
pin connections, 3-15 to 3-16
signal assignments (table), 3-16
timing specifications, 3-16 to 3-17
status-word bit definitions
Mode 1 input, E-28
Mode 1 output, E-30
Mode 2 operation, E-32
posttrigger data acquisition timing
(figure), 3-22
posttrigger mode
controlled acquisition mode
programming, E-12 to E-14
freerun acquisition mode
programming, E-16
initiation of multiple A/D conversions using
EXTTRIG signal, E-11
power requirement specifications, A-6