National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ - Manual (Page 172)

Register-Level Programming Appendix E
Lab-PC+ User Manual E-16 © National Instruments Corporation
5. Start and service the data acquisition operation.
To start the data acquisition operation, set the SWTRIG bit in Command Register 2. After
this setting, A/D conversions are initiated by a falling edge on EXTCONV* input, but the
sample counter (Counter A1) is not gated on until a rising edge on EXTTRIG input. After a
rising edge on EXTTRIG input is sensed, A/D conversions remain enabled for the
programmed count, after which GATA0 is set low and EXTCONV* input is disabled. The
operation must be serviced by reading the A/D FIFO Register every time an A/D conversion
result becomes available. To service the data acquisition, perform the following sequence
until GATA0 bit in the Status Register is set low:
a. Read the Status Register (8-bit read).
b. If the DAVAIL bit is set (bit 0), read the A/D FIFO Register to obtain the result.
DMA or interrupts can also be used to service the data acquisition operation. These topics are
discussed in the A/D Interrupt Programming and Programming DMA Operation sections later in
this appendix.
Two error conditions may occur during a data acquisition operation: an overflow error or an
overrun error. These error conditions are reported through the Status Register and should be
checked every time the Status Register is read to check the DAVAIL bit.
An overflow condition occurs if more than 16 A/D conversions have been stored in the A/D
FIFO without the A/D FIFO being read; that is, the A/D FIFO is full and cannot accept any more
data. This condition occurs if the software loop reading the A/D FIFO Register is not fast
enough to keep up with the A/D conversion rate. When an overflow occurs, at least one A/D
conversion result is lost. An overflow condition has occurred if the OVERFLOW bit in the
Status Register is cleared.
An overrun condition occurs if a second A/D conversion is initiated before the previous
conversion is finished. This condition may result in one or more missing A/D conversions. This
condition occurs if the sample interval is too small (sample rate is too high). An overrun
condition has occurred if the OVERRUN bit in the Status Register is low. The minimum
recommended sampling interval on the Lab-PC+ is 16
µ
s.
Both the OVERFLOW and OVERRUN bits in the Status Register are reset by writing to the A/D
Clear Register.
Programming in Freerun Acquisition Mode
Posttrigger Mode
A posttrigger data acquisition in freerun acquisition mode using EXTCONV* requires a
programming sequence similar to controlled acquisition mode, except that steps 5b and 5c are
not performed. The sample count is kept in software and conversions remain enabled until
GATA0 is set low. GATA0 can be set low by writing 34 (hex) to the Counter A Mode Register
after the required number of samples is obtained. This disables EXTCONV*, that is, further
transitions on EXTCONV* are ignored.