Scanclk signal, Extstrobe* signal, Figure 4-18. typical pretriggered acquisition – National Instruments PCI-6023E User Manual
Page 62: Figure 4-19. scanclk signal timing, Scanclk signal -33 extstrobe* signal -33, Figure 4-18, Typical pretriggered acquisition -33, Figure 4-19, Scanclk signal timing -33, Shows the timing for the scanclk signal
Chapter 4
Signal Connections
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National Instruments Corporation
4-33
PCI-6023E/6024E/6025E User Manual
Figure 4-18. Typical Pretriggered Acquisition
SCANCLK Signal
SCANCLK is an output-only signal that generates a pulse with the leading
edge occurring approximately 50 to 100 ns after an A/D conversion begins.
The polarity of this output is software-selectable but is typically configured
so that a low-to-high leading edge can clock external analog input
multiplexers indicating when the input signal has been sampled and can be
removed. This signal has a 400 to 500 ns pulse width and is
software-enabled. Figure 4-19
shows the timing for the SCANCLK signal.
Figure 4-19. SCANCLK Signal Timing
EXTSTROBE* Signal
EXTSTROBE* is an output-only signal that generates either a single pulse
or a sequence of eight pulses in the hardware-strobe mode. An external
device can use this signal to latch signals or to trigger events. In the
single-pulse mode, software controls the level of the EXTSTROBE*
signal. A 10 µs and a 1.2 µs clock are available for generating a sequence
of eight pulses in the hardware-strobe mode. Figure 4-20 shows the timing
for the hardware-strobe mode EXTSTROBE* signal.
Don't Care
0
1
2
3
1
0
2
2
2
TRIG1
TRIG2
STARTSCAN
CONVERT*
Scan Counter
t
w
t
w
= 400 to 500 ns
t
d
= 50 to 100 ns
t
d
CONVERT*
SCANCLK
PCI.book Page 33 Wednesday, September 16, 1998 9:09 AM