B&B Electronics Zlinx ZP Series - Manual (Page 36)

32 Manual Documentation Number: ZP24D-250RM-SR-2508
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IR (v1.xA0*) I/O Settings
Sample Rate. Set/Read sample
rate. When set, this parameter
causes the module to sample all
enabled inputs at a specified
interval.
0 -0xFFFF [x 1
msec]
0
AV (v1.xA0*) I/O Settings
ADC Voltage Reference.
Set/Read ADC reference voltage
switch. 0 – 1
0 = VREF pin
1 = Internal
0
IA (v1.xA0*)
I/O Settings {I/O
Line Passing}
I/O Input Address. Set/Read
addresses of module to which
outputs are bound. Setting all
bytes to 0xFF will not allow any
received I/O packet to change
outputs. Setting address to
0xFFFF will allow any received
I/O packet to change outputs.
0 -
0xFFFFFFFFFFFF
FFFF
0xFFFFFF
F
FFFFFFFF
F
T0 - T7
(v1.xA0*) I/O Settings {I/O
Line Passing}
(D0 - D7) Output Timeout.
Set/Read Output timeout values
for lines that correspond with the
D0 - D7 parameters. When output
is set (due to I/O line passing) to
a non-default level, a timer is
started which when expired will
set the output to it default level.
The timer is reset when a valid
I/O packet is received.
0 - 0xFF
[x 100 ms]
0xFF
P0
I/O Settings {I/O
Line Passing}
PWM0 Configuration.
Select/Read function for PWM0
pin.
0 – 2
0 = Disabled
1 = RSSI
2 = PWM Output
1
P1 (v1.xA0*)
I/O Settings {I/O
Line Passing}
PWM1 Configuration.
Select/Read function for PWM1
pin.
0 – 2
0 = Disabled
1 = RSSI
2 = PWM Output
0
M0 (v1.xA0*)
I/O Settings {I/O
Line Passing} PWM0 Output Level. Set/Read
the PWM0 output level.
0 - 0x03FF -
M1 (v1.xA0*)
I/O Settings {I/O
Line Passing} PWM1 Output Level. Set/Read
the PWM0 output level.
0 - 0x03FF -
PT (v1.xA0*)
I/O Settings {I/O
Line Passing}
PWM Output Timeout. Set/Read
output timeout value for both
PWM outputs. When PWM is set
to a non-zero value: Due to I/O
line passing, a time is started
which when expired will set the
PWM output to zero. The timer is
reset when a valid I/O packet is
received.]
0 - 0xFF
[x 100 ms]
0xFF
RP
I/O Settings {I/O
Line Passing}
RSSI PWM Timer.Set/Read
PWM timer register. Set the
duration of PWM (pulse width
modulation) signal output on the
RSSI pin. The signal duty cycle is
updated with each received
packet and is shut off when the
timer expires.]
0 - 0xFF
[x 100 ms]
0x28 (40d)