Rockwell Automation 1771-VHSC , D17716.5.74 Very High S - Manual (Page 49)

5–3 Module Status and Input Data
Table 5.B provides bit/word descriptions for the block transfer read
instruction returned by the 1771-VHSC module to the processor.
Table 5.B
Bit/Word Description for the VHSC Module (1771ĆVHSC)
Word Bit Definition
Bit 00
PowerĆup bit indicates whether a successful BTW with valid data has
occurred since powerup, or since last switched from Program to Run
mode.
Bit = 0 Ć A successful BTW has occurred
Bit = 1 Ć A successful BTW has not occurred
Word 1
Bits 01Ć03 Not used
Bits 04Ć07
New data bits. Indicates that a store register (BTR words 11Ć18) has
been updated. These bits are reset by a 0 to 1 transition of the new
data acknowledge bits in BTW word 1, bits 4Ć7. Bit 04 corresponds to
counter 0, bit 05 to counter 1, etc.
Bits 08Ć15
(Bits 10Ć17)
Diagnostic byte. Always in BCD. This byte indicates the number of the
first word in the BTW file that was incorrect. Refer to chapter 7 for
other diagnostic error codes returned by the module.
Bits 00Ć07
Status bits for outputs. Bit 00 corresponds to output 0, bit 01 to
counter 2, etc.
Bit = 0 Ć output OFF
Bit = 1 Ć output ON
Word 2
Bits 08Ć11
(Bits 10Ć12)
State of gate/reset input. Bit 08 (10) corresponds to counter 0,
bit 09 (11) to counter 1, etc.
Bit = 0 Ć gate input inactive
Bit = 1 Ć gate input active
Bits 12Ć15
(Bits 13Ć17)
Not used
Word 3
Contains the most significant digit for counter 0. The allowable range
is 0Ć999.
Word 4
Contains the least significant digit for counter 0. The allowable range
is 0Ć999.
Word 5
Contains the most significant digit for counter 1. The allowable range
is 0Ć999.
Word 6
Contains the least significant digit for counter 1. The allowable range
is 0Ć999.
Word 7
Contains the most significant digit for counter 2. The allowable range
is 0Ć999.
Word 8
Contains the least significant digit for counter 2. The allowable range
is 0Ć999.
Word 9
Contains the most significant digit for counter 3. The allowable range
is 0Ć999.
Word 10
Contains the least significant digit for counter 3. The allowable range
is 0Ć999.
Words 11
Counter 0 Store count values MSD (range 0Ć999) in encoder/counter
mode; or frequency value MSD (range 0Ć500) in rate measurement or
period/rate mode
Bit/Word Description for
Block Transfer Read