ADLINK PXI-2006 - Manual (Page 38)

28 Operation Theory
DAQ/PXI-2010 AI Data Format
Synchronous Digital Inputs (for DAQ/PXI-2010 only)
When each A/D conversion is completed, the 14-bits converted
digital data accompanied with 2 bits of SDI<1..0>_X per chan-
nel from J5 will be latched into the 16-bit register and data
FIFO, as shown in Figure 8 and Figure 9. Therefore, users can
simultaneously sample one analog signal with four digital sig-
nals. The data format of every acquired 16-bit data is as fol-
lows:
D13, D12, D11 ....... D1, D0, b1, b0
Where
D13, D12, D11 ....... D1, D0: 2’s complement A/D
14-bit data
b1, b0: Synchronous Digital Inputs SDI<1..0>
Figure 4-1: Synchronous Digital Inputs Block Diagram
Figure 4-2: Synchronous Digital Inputs timing
Note: Since the analog signal is sampled when an A/D conversion
starts (falling edge of A/D_conversion signal), while
SDI<1..0> are sam-pled right after an A/D conversion com-
pletes (rising edge of nADBUSY signal). Precisely SDI<1..0>
are sampled within 220 to 400ns lag to the analog signal,