ADLINK PXI-2006 - Manual (Page 8)

iv List of Figures
List of Figures
Figure 2-1: PCB Layout of the DAQ-20XX................................. 17
Figure 2-2: PCB Layout of the PXI-20XX................................... 17
Figure 3-1: Single-Ended connections ....................................... 25
Figure 3-2: Ground-referenced source and differential input ..... 25
Figure 3-3: Floating source and differential input....................... 26
Figure 4-1: Synchronous Digital Inputs Block Diagram.............. 28
Figure 4-2: Synchronous Digital Inputs timing ........................... 28
Figure 4-3: Scan Timing............................................................. 32
Figure 4-4: Pre-trigger (trigger occurs after at least M scans ac-
quired) ..................................................................... 34
Figure 4-5: Pre-trigger scan acquisition (trigger occurs when a con-
version is in progress).............................................. 34
Figure 4-6: Pre-trigger with M_enable = 0 (Trigger occurs before M
scans) ...................................................................... 35
Figure 4-7: Pre-trigger with M_enable = 1 ................................. 35
Figure 4-8: Middle trigger with M_enable = 1............................. 36
Figure 4-9: Middle trigger (trigger occurs when a scan is in progress)
37
Figure 4-10: Post trigger .............................................................. 38
Figure 4-11: Delay trigger ............................................................ 39
Figure 4-12: Post trigger with re-trigger ....................................... 40
Figure 4-13: Scatter/gather DMA for data transfer....................... 42
Figure 4-14: Typical D/A timing of waveform generation (Assuming
the data in the data buffer are 2V, 4V, -4V, 0V)....... 45
Figure 4-15: Post trigger waveform generation (Assuming the data in
the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) 46
Figure 4-16: Delay trigger waveform generation (Assuming the data in
the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) 47
Figure 4-17: Re-triggered waveform generation (Assuming the data in
the data buffer are 2V, 4V, 2V, 0V).......................... 47
Figure 4-18: Finite iterative waveform generation with Post-trigger and
DLY2_Counter = 0 (Assuming the data in the data buffer
are 2V, 4V, 2V, 0V).................................................. 48
Figure 4-19: Infinite iterative waveform generation with Post-trigger
and DLY2_Counter = 0 (Assuming the data in the data
buffer are 2V, 4V, 2V, 0V)........................................ 49
Figure 4-20: Stop mode I (Assuming the data in the data buffer are 2V,
4V, 2V, 0V) .............................................................. 50