ADLINK PXI-2006 - Manual (Page 54)

44 Operation Theory
bipolar, and ref-erence source: internal 10V or external AOEX-
TREF. Then update the digital values into D/A data registers
through a software output command.
Timed Waveform Generation
This mode can provide your applications with a precise D/A output
with a fixed update rate. It can be used to generate an infinite or
finite waveform. You can accurately program the update period of
the D/A converters.
The D/A output timing is provided through a combination of
counters in the FPGA on board. There are totally 5 counters to be
specified. These counters are:
UI_counter (24 bits): specify the DA Update
Interval = CHUI_counter/TIMEBASE.
UC_counter (24 bits): specify the total Update
Counts in a single waveform
IC_counter (24 bits): specify the Iteration
Counts of waveform.
DA_DLY1_counter (16 bits): specify the Delay from
the trigger to the first update start.
DA_DLY2_counter (16 bits): specify the Delay
between two consecutive waveform
generations.