ADLINK PXI-2006 - Manual (Page 50)

40 Operation Theory
Figure 4-12: Post trigger with re-trigger
Bus-mastering DMA Data Transfer
PCI bus-mastering DMA is necessary for high speed DAQ in
order to utilize the maximum PCI bandwidth. The bus-master-
ing controller, which is built in the PLX IOP-480 PCI controller,
controls the PCI bus when it becomes the master of the bus.
Bus mastering reduces the size of the on-board memory and
reduces the CPU loading because data is directly transferred
to the computer’s memory without host CPU intervention.
Bus-mastering DMA provides the fastest data transfer rate on
PCI-bus. Once the analog input operation starts, control
returns to your program. The hardware temporarily stores the
acquired data in the on-board AD Data FIFO and then transfers
the data to a user-defined DMA buffer memory in the computer.
Please note that even when the acquired data length is less
than the Data FIFO, the AD data will not be kept in the Data
FIFO but directly transferred into host memory by the bus-mas-
tering DMA.
The DMA transfer mode is very complex to program. We rec-
ommend using a high-level program library to configure this
card. If users would like to know more about programs/soft-
ware’s that can handle the DMA bus master data transfer,