Altera QDRII SRAM Controller MegaCore Function - Manual (Page 21)

Altera Corporation MegaCore Version 9.1 2–11
November 2009 QDRII SRAM Controller MegaCore Function User Guide
Getting Started
Simulate the
Example Design This section describes the following simulation techniques:
■ Simulate with IP Functional Simulation Models
■ Simulating With the ModelSim Simulator
■ Simulating With Other Simulators
■ Simulating in Third-Party Simulation Tools Using NativeLink
Simulate with IP Functional Simulation Models
You can simulate the example design using the IP Toolbench-generated IP
functional simulation models. IP Toolbench generates a VHDL or Verilog
HDL testbench for your example design, which is in the testbench
directory in your project directory.
f
For more information on the testbench, refer to “Example Design” on
page 3–27 .
You can use the IP functional simulation model with any
Altera-supported VHDL or Verilog HDL simulator. The instructions for
the ModelSim simulator are different to other simulators.
Simulating With the ModelSim Simulator
Altera supplies a generic memory model, lib\qdrii_model.v, which
allows you to simulate the example design with the ModelSim simulator.
To simulate the example design with the ModelSim
® simulator, follow
these steps:
1. Copy the generic memory model to the <directory name>\testbench
directory.
2. Open the memory model and the testbench (<top-level
name>_vsim.v or .vhd) in a text editor and ensure the signal names
have the same capitalization in both files.
3. Start the ModelSim-Altera simulator.
4. Change your working directory to your IP Toolbench-generated file
directory <directory name>\testbench\modelsim.
5. To simulate with an IP functional simulation model simulation, type
the following command:
source <variation name>_vsim.tcl r