Compile the example design, Compile the example design –19, Compile the – Altera QDRII SRAM Controller MegaCore Function User Manual
Page 29
Altera Corporation
MegaCore Version 9.1
2–19
November 2009
QDRII SRAM Controller MegaCore Function User Guide
Getting Started
To edit the example PLL, follow these steps:
1.
Choose MegaWizard Plug-In Manager (Tools menu).
2.
Select Edit an existing custom megafunction variation and click
Next
.
3.
In your Quartus II project directory, for VHDL choose
qdrii_pll_
<device name>.vhd; for Verilog HDL choose
qdrii_pll_
<device name>.v.
4.
Click Next.
5.
Edit the PLL parameters in the altpll MegaWizard Plug-In.
f
For more information on the altpll megafunction, refer to the
Quartus II Help or click Documentation in the altpll MegaWizard
Plug-In.
Compile the
Example Design
Before the Quartus II software compiles the example design it runs the IP
Toolbench-generated Tcl constraints script, auto_add_constraints.tcl.
The auto_add_qdrii_constraints.tcl script calls the
add_constraints_for_
<variation name>.tcl script for each variation in your
design. The add_constraints_for_<variation name>.tcl script checks for
any previously added constraints, removes them, and then adds
constraints for that variation.
The constraints script analyzes and elaborates your design, to
automatically extract the hierarchy to your variation. To prevent the
constraints script analyzing and elaborating your design, turn on Enable
hierarchy control
in the wizard, and enter the correct hierarchy path to
your data path (refer to step
).
When the constraints script runs, it creates another script,
remove_constraints_for_
<variation name>.tcl, which you can use to
remove the constraints from your design.
To compile the example instance, follow these steps:
1.
Optional. Enable TimeQuest Timing Analyzer.
a.
On the Assignments menu click Settings, expand Timing
Analysis Settings
, and select Use TimeQuest Timing
Analyzer
.