Simulating with other simulators, Vhdl ip functional simulations – Altera QDRII SRAM Controller MegaCore Function User Manual
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MegaCore Version 9.1
Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide
November 2009
Simulate the Example Design
6.
For a gate-level timing simulation (VHDL or Verilog HDL
ModelSim output from the Quartus II software), type the following
commands:
set use_gate_model 1
r
source
<variation name>_vsim.tcl
r
Simulating With Other Simulators
The IP Toollbench-generated Tcl script is for the ModelSim simulator
only. If you prefer to use a different simulation tool, follow these
instructions. You can also use the generated script as a guide. You also
need to download and compile an appropriate memory model.
1
The following variables apply in this section:
●
<QUARTUS ROOTDIR> is the Quartus II installation directory
●
<simulator name> is the name of your simulation tool
●
<device name> is the Altera device family name
●
<project name> is the name of your Quartus II top-level entity or
module.
●
<MegaCore install directory> is the QDRII SRAM Controller
installation directory
VHDL IP Functional Simulations
For VHDL simulations with IP functional simulation models, follow
these steps:
1.
Create a directory in the <project directory>\testbench directory.
2.
Launch your simulation tool inside this directory and create the
following libraries:
●
altera_mf
●
lpm
●
sgate
●
<device name>
●
auk_qdrii_lib