Altera QDRII SRAM Controller MegaCore Function - Manual (Page 47)

Altera Corporation MegaCore Version 9.1 3–15
November 2009 QDRII SRAM Controller MegaCore Function User Guide
Functional Description
Figure 3–11. Write Burst with Pause—Burst of Four (Narrow Mode)
For a burst of four (wide mode), you cannot transfer more than one write
request every other cycle, because it takes two cycles on the QDRII SRAM
side to send the data. Therefore, if two consecutive writes arrive, the
controller pauses the second one for one clock cycle.
Reads
This section discusses the following topics:
■ “Isolated Read” on page 3–15
■ “Burst” on page 3–17
■ “Bursts with Pauses” on page 3–18
Isolated Read
Figure 3–12 on page 3–16 shows a read request from the Avalon read
interface for a burst of four. The Avalon read FSM issues a latent read and
transfers the data back at a later stage, which frees the Avalon interface.
The controller transfers the read to the QDRII SRAM. A few cycles later
(timing is not accurate), the data arrives, in synchronization with the cq
and cqN clocks. Even though only one set of data was requested, the
memory send two sets of data. The controller captures and
resynchronizes the data onto the system clock and it appears on the
Avalon interface a few cycles later. The controller asserts
avl_data_read_valid
with the data to validate the data cycle.
write
avl_data_wr
[35:0]
avl_addr_wr
[19:0]
avl_wait_
request_wr
system_clk
qdrii_d[17:0]
qdrii_a[19:0]
qdrii_bwsn[1:0]
qdrii_wpsn
00010002 11031104 11051106 11051106
0001 1122 1123
0001 0002 1103 1104 1105 1106 1106
0001 1122
00 11 00 00
avl_clk
avl_clock_wr