Altera QDRII SRAM Controller MegaCore Function - Manual (Page 24)

2–14 MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide November 2009
Simulate the Example Design
4. Set the Tcl variable gRTL_DELAYS to 1, which tells the testbench to
model the extra delays in the system necessary for RTL simulation
5. Load the testbench in your simulator with the timestep set to
picoseconds.
VHDL Gate-Level Simulations
For VHDL simulations with gate-level models, follow these steps:
1. Create a directory in the <project directory>\testbench directory.
2. Launch your simulation tool inside this directory and create the
following libraries.
● <device name>
● auk_qdrii_lib
3. Compile the files in Table 2–3 into the appropriate library. The files
are in VHDL93 format.
4. Set the Tcl variable gRTL_DELAYS to 0, which tells the testbench not
to use the insert extra delays in the system, because these are
applied inside the gate-level model.
5. Load the testbench in your simulator with the timestep set to
picoseconds.
Verilog HDL IP Functional Simulations
For Verilog HDL simulations with IP functional simulation models,
follow these steps:
1. Create a directory in the <project directory>\testbench directory.
2. Launch your simulation tool inside this directory and create the
following libraries.:
Table 2–3. Files to Compile—VHDL Gate-Level Simulations
Library Filename
<device name> <QUARTUS ROOTDIR>/eda/sim_lib/<device name>_atoms.vhd
<QUARTUS ROOTDIR>/eda/sim_lib/<device name>_components.vhd
auk_qdrii_lib <project directory>/simulation/<simulator name>/<project name>.vho
<project directory>/testbench/<project name>_tb.vhd