Document Outline

• Revision History
• List of Chapters
• Table of Contents
• Chapter 1 General Description
  • 1.1 Introduction
  • 1.2 Features
  • 1.3 MCU Block Diagram
  • 1.4 Pin Assignments
    • 1.4.1 Power Supply Pins (VDD and VSS)
    • 1.4.2 Oscillator Pins (OSC1 and OSC2)
    • 1.4.3 External Reset Pin (RST)
    • 1.4.4 External Interrupt Pin (IRQ)
    • 1.4.5 CGM Power Supply Pins (VDDA and VSSAD)
    • 1.4.6 External Filter Capacitor Pin (CGMXFC)
    • 1.4.7 Analog Power Supply Pins (VDDAD and VSSAD)
    • 1.4.8 ADC Voltage Decoupling Capacitor Pin (VREFH)
    • 1.4.9 ADC Voltage Reference Low Pin (VREFL)
    • 1.4.10 Port A Input/Output (I/O) Pins (PTA7-PTA0)
    • 1.4.11 Port B I/O Pins (PTB7/ATD7-PTB0/ATD0)
    • 1.4.12 Port C I/O Pins (PTC6-PTC2 and PTC1/ATD9-PTC0/ATD8)
    • 1.4.13 Port D Input-Only Pins (PTD6/IS3-PTD4/IS1 and PTD3/FAULT4-PTD0/FAULT1)
    • 1.4.14 PWM Pins (PWM6-PWM1)
    • 1.4.15 PWM Ground Pin (PWMGND)
    • 1.4.16 Port E I/O Pins (PTE7/TCH3A-PTE3/TCLKA and PTE2/TCH1B-PTE0/TCLKB)
    • 1.4.17 Port F I/O Pins (PTF5/TxD-PTF4/RxD and PTF3/MISO-PTF0/SPSCK)
• Chapter 2 Memory
  • 2.1 Introduction
  • 2.2 Unimplemented Memory Locations
  • 2.3 Reserved Memory Locations
  • 2.4 I/O Section
  • 2.5 Memory Map
  • 2.6 Monitor ROM
  • 2.7 Random-Access Memory (RAM)
  • 2.8 FLASH Memory (FLASH)
    • 2.8.1 FLASH Control Register
    • 2.8.2 FLASH Page Erase Operation
    • 2.8.3 FLASH Mass Erase Operation
    • 2.8.4 FLASH Program Operation
    • 2.8.5 FLASH Block Protection
    • 2.8.6 FLASH Block Protect Register
    • 2.8.7 Wait Mode
    • 2.8.8 Stop Mode
• Chapter 3 Analog-to-Digital Converter (ADC)
  • 3.1 Introduction
  • 3.2 Features
  • 3.3 Functional Description
    • 3.3.1 ADC Port I/O Pins
    • 3.3.2 Voltage Conversion
    • 3.3.3 Conversion Time
    • 3.3.4 Continuous Conversion
    • 3.3.5 Result Justification
    • 3.3.6 Monotonicity
  • 3.4 Interrupts
  • 3.5 Wait Mode
  • 3.6 I/O Signals
    • 3.6.1 ADC Analog Power Pin (VDDAD)
    • 3.6.2 ADC Analog Ground Pin (VSSAD)
    • 3.6.3 ADC Voltage Reference Pin (VREFH)
    • 3.6.4 ADC Voltage Reference Low Pin (VREFL)
    • 3.6.5 ADC Voltage In (ADVIN)
    • 3.6.6 ADC External Connections
      • 3.6.6.1 VREFH and VREFL
      • 3.6.6.2 ANx
      • 3.6.6.3 Grounding
  • 3.7 I/O Registers
    • 3.7.1 ADC Status and Control Register
    • 3.7.2 ADC Data Register High
    • 3.7.3 ADC Data Register Low
    • 3.7.4 ADC Clock Register
• Chapter 4 Clock Generator Module (CGM)
  • 4.1 Introduction
  • 4.2 Features
  • 4.3 Functional Description
    • 4.3.1 Crystal Oscillator Circuit
    • 4.3.2 Phase-Locked Loop Circuit (PLL)
      • 4.3.2.1 PLL Circuits
      • 4.3.2.2 Acquisition and Tracking Modes
      • 4.3.2.3 Manual and Automatic PLL Bandwidth Modes
      • 4.3.2.4 Programming the PLL
      • 4.3.2.5 Special Programming Exceptions
    • 4.3.3 Base Clock Selector Circuit
    • 4.3.4 CGM External Connections
  • 4.4 I/O Signals
    • 4.4.1 Crystal Amplifier Input Pin (OSC1)
    • 4.4.2 Crystal Amplifier Output Pin (OSC2)
    • 4.4.3 External Filter Capacitor Pin (CGMXFC)
    • 4.4.4 PLL Analog Power Pin (VDDA)
    • 4.4.5 Oscillator Enable Signal (SIMOSCEN)
    • 4.4.6 Crystal Output Frequency Signal (CGMXCLK)
    • 4.4.7 CGM Base Clock Output (CGMOUT)
    • 4.4.8 CGM CPU Interrupt (CGMINT)
  • 4.5 CGM Registers
    • 4.5.1 PLL Control Register
    • 4.5.2 PLL Bandwidth Control Register
    • 4.5.3 PLL Programming Register
  • 4.6 Interrupts
  • 4.7 Wait Mode
  • 4.8 Acquisition/Lock Time Specifications
    • 4.8.1 Acquisition/Lock Time Definitions
    • 4.8.2 Parametric Influences on Reaction Time
    • 4.8.3 Choosing a Filter Capacitor
    • 4.8.4 Reaction Time Calculation
• Chapter 5 Configuration Register (CONFIG)
  • 5.1 Introduction
  • 5.2 Functional Description
  • 5.3 Configuration Register
• Chapter 6 Computer Operating Properly (COP)
  • 6.1 Introduction
  • 6.2 Functional Description
  • 6.3 I/O Signals
    • 6.3.1 CGMXCLK
    • 6.3.2 COPCTL Write
    • 6.3.3 Power-On Reset
    • 6.3.4 Internal Reset
    • 6.3.5 Reset Vector Fetch
    • 6.3.6 COPD (COP Disable)
  • 6.4 COP Control Register
  • 6.5 Interrupts
  • 6.6 Monitor Mode
  • 6.7 Wait Mode
  • 6.8 Stop Mode
• Chapter 7 Central Processor Unit (CPU)
  • 7.1 Introduction
  • 7.2 Features
  • 7.3 CPU Registers
    • 7.3.1 Accumulator
    • 7.3.2 Index Register
    • 7.3.3 Stack Pointer
    • 7.3.4 Program Counter
    • 7.3.5 Condition Code Register
  • 7.4 Arithmetic/Logic Unit (ALU)
  • 7.5 Low-Power Modes
    • 7.5.1 Wait Mode
    • 7.5.2 Stop Mode
  • 7.6 CPU During Break Interrupts
  • 7.7 Instruction Set Summary
  • 7.8 Opcode Map
• Chapter 8 External Interrupt (IRQ)
  • 8.1 Introduction
  • 8.2 Features
  • 8.3 Functional Description
  • 8.4 IRQ Pin
  • 8.5 IRQ Status and Control Register
• Chapter 9 Low-Voltage Inhibit (LVI)
  • 9.1 Introduction
  • 9.2 Features
  • 9.3 Functional Description
    • 9.3.1 Polled LVI Operation
    • 9.3.2 Forced Reset Operation
    • 9.3.3 False Reset Protection
    • 9.3.4 LVI Trip Selection
  • 9.4 LVI Status and Control Register
  • 9.5 LVI Interrupts
  • 9.6 Wait Mode
  • 9.7 Stop Mode
• Chapter 10 Input/Output (I/O) Ports (PORTS)
  • 10.1 Introduction
  • 10.2 Port A
    • 10.2.1 Port A Data Register
    • 10.2.2 Data Direction Register A
  • 10.3 Port B
    • 10.3.1 Port B Data Register
    • 10.3.2 Data Direction Register B
  • 10.4 Port C
    • 10.4.1 Port C Data Register
    • 10.4.2 Data Direction Register C
  • 10.5 Port D
  • 10.6 Port E
    • 10.6.1 Port E Data Register
    • 10.6.2 Data Direction Register E
  • 10.7 Port F
    • 10.7.1 Port F Data Register
    • 10.7.2 Data Direction Register F
• Chapter 11 Power-On Reset (POR)
  • 11.1 Introduction
  • 11.2 Functional Description
• Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC)
  • 12.1 Introduction
  • 12.2 Features
  • 12.3 Timebase
    • 12.3.1 Resolution
    • 12.3.2 Prescaler
  • 12.4 PWM Generators
    • 12.4.1 Load Operation
    • 12.4.2 PWM Data Overflow and Underflow Conditions
  • 12.5 Output Control
    • 12.5.1 Selecting Six Independent PWMs or Three Complementary PWM Pairs
    • 12.5.2 Dead-Time Insertion
    • 12.5.3 Top/Bottom Correction with Motor Phase Current Polarity Sensing
    • 12.5.4 Output Polarity
    • 12.5.5 PWM Output Port Control
  • 12.6 Fault Protection
    • 12.6.1 Fault Condition Input Pins
      • 12.6.1.1 Fault Pin Filter
      • 12.6.1.2 Automatic Mode
      • 12.6.1.3 Manual Mode
    • 12.6.2 Software Output Disable
    • 12.6.3 Output Port Control
  • 12.7 Initialization and the PWMEN Bit
  • 12.8 PWM Operation in Wait Mode
  • 12.9 Control Logic Block
    • 12.9.1 PWM Counter Registers
    • 12.9.2 PWM Counter Modulo Registers
    • 12.9.3 PWMx Value Registers
    • 12.9.4 PWM Control Register 1
    • 12.9.5 PWM Control Register 2
    • 12.9.6 Dead-Time Write-Once Register
    • 12.9.7 PWM Disable Mapping Write-Once Register
    • 12.9.8 Fault Control Register
    • 12.9.9 Fault Status Register
    • 12.9.10 Fault Acknowledge Register
    • 12.9.11 PWM Output Control Register
  • 12.10 PWM Glossary
• Chapter 13 Serial Communications Interface Module (SCI)
  • 13.1 Introduction
  • 13.2 Features
  • 13.3 Functional Description
    • 13.3.1 Data Format
    • 13.3.2 Transmitter
      • 13.3.2.1 Character Length
      • 13.3.2.2 Character Transmission
      • 13.3.2.3 Break Characters
      • 13.3.2.4 Idle Characters
      • 13.3.2.5 Inversion of Transmitted Output
      • 13.3.2.6 Transmitter Interrupts
    • 13.3.3 Receiver
      • 13.3.3.1 Character Length
      • 13.3.3.2 Character Reception
      • 13.3.3.3 Data Sampling
      • 13.3.3.4 Framing Errors
      • 13.3.3.5 Receiver Wakeup
      • 13.3.3.6 Receiver Interrupts
      • 13.3.3.7 Error Interrupts
  • 13.4 Wait Mode
  • 13.5 SCI During Break Module Interrupts
  • 13.6 I/O Signals
    • 13.6.1 PTF5/TxD (Transmit Data)
    • 13.6.2 PTF4/RxD (Receive Data)
  • 13.7 I/O Registers
    • 13.7.1 SCI Control Register 1
    • 13.7.2 SCI Control Register 2
    • 13.7.3 SCI Control Register 3
    • 13.7.4 SCI Status Register 1
    • 13.7.5 SCI Status Register 2
    • 13.7.6 SCI Data Register
    • 13.7.7 SCI Baud Rate Register
• Chapter 14 System Integration Module (SIM)
  • 14.1 Introduction
  • 14.2 SIM Bus Clock Control and Generation
    • 14.2.1 Bus Timing
    • 14.2.2 Clock Startup from POR or LVI Reset
    • 14.2.3 Clocks in Wait Mode
  • 14.3 Reset and System Initialization
    • 14.3.1 External Pin Reset
    • 14.3.2 Active Resets from Internal Sources
      • 14.3.2.1 Power-On Reset (POR)
      • 14.3.2.2 Computer Operating Properly (COP) Reset
      • 14.3.2.3 Illegal Opcode Reset
      • 14.3.2.4 Illegal Address Reset
      • 14.3.2.5 Forced Monitor Mode Entry Reset (MENRST)
      • 14.3.2.6 Low-Voltage Inhibit (LVI) Reset
  • 14.4 SIM Counter
    • 14.4.1 SIM Counter During Power-On Reset
    • 14.4.2 SIM Counter and Reset States
  • 14.5 Exception Control
    • 14.5.1 Interrupts
      • 14.5.1.1 Hardware Interrupts
      • 14.5.1.2 Software Interrupt (SWI) Instruction
    • 14.5.2 Reset
  • 14.6 Low-Power Mode
    • 14.6.1 Wait Mode
    • 14.6.2 Stop Mode
  • 14.7 SIM Registers
    • 14.7.1 SIM Break Status Register
    • 14.7.2 SIM Reset Status Register
    • 14.7.3 SIM Break Flag Control Register
• Chapter 15 Serial Peripheral Interface Module (SPI)
  • 15.1 Introduction
  • 15.2 Features
  • 15.3 Pin Name Conventions
  • 15.4 Functional Description
    • 15.4.1 Master Mode
    • 15.4.2 Slave Mode
  • 15.5 Transmission Formats
    • 15.5.1 Clock Phase and Polarity Controls
    • 15.5.2 Transmission Format When CPHA = 0
    • 15.5.3 Transmission Format When CPHA = 1
    • 15.5.4 Transmission Initiation Latency
  • 15.6 Error Conditions
    • 15.6.1 Overflow Error
    • 15.6.2 Mode Fault Error
  • 15.7 Interrupts
  • 15.8 Resetting the SPI
  • 15.9 Queuing Transmission Data
  • 15.10 Low-Power Mode
  • 15.11 I/O Signals
    • 15.11.1 MISO (Master In/Slave Out)
    • 15.11.2 MOSI (Master Out/Slave In)
    • 15.11.3 SPSCK (Serial Clock)
    • 15.11.4 SS (Slave Select)
    • 15.11.5 VSS (Clock Ground)
  • 15.12 I/O Registers
    • 15.12.1 SPI Control Register
    • 15.12.2 SPI Status and Control Register
    • 15.12.3 SPI Data Register
• Chapter 16 Timer Interface A (TIMA)
  • 16.1 Introduction
  • 16.2 Features
  • 16.3 Functional Description
    • 16.3.1 TIMA Counter Prescaler
    • 16.3.2 Input Capture
    • 16.3.3 Output Compare
      • 16.3.3.1 Unbuffered Output Compare
      • 16.3.3.2 Buffered Output Compare
    • 16.3.4 Pulse-Width Modulation (PWM)
      • 16.3.4.1 Unbuffered PWM Signal Generation
      • 16.3.4.2 Buffered PWM Signal Generation
      • 16.3.4.3 PWM Initialization
  • 16.4 Interrupts
  • 16.5 Wait Mode
  • 16.6 I/O Signals
    • 16.6.1 TIMA Clock Pin (PTE3/TCLKA)
    • 16.6.2 TIMA Channel I/O Pins (PTE4/TCH0A-PTE7/TCH3A)
  • 16.7 I/O Registers
    • 16.7.1 TIMA Status and Control Register
    • 16.7.2 TIMA Counter Registers
    • 16.7.3 TIMA Counter Modulo Registers
    • 16.7.4 TIMA Channel Status and Control Registers
    • 16.7.5 TIMA Channel Registers
• Chapter 17 Timer Interface B (TIMB)
  • 17.1 Introduction
  • 17.2 Features
  • 17.3 Functional Description
    • 17.3.1 TIMB Counter Prescaler
    • 17.3.2 Input Capture
    • 17.3.3 Output Compare
      • 17.3.3.1 Unbuffered Output Compare
      • 17.3.3.2 Buffered Output Compare
    • 17.3.4 Pulse-Width Modulation (PWM)
      • 17.3.4.1 Unbuffered PWM Signal Generation
      • 17.3.4.2 Buffered PWM Signal Generation
      • 17.3.4.3 PWM Initialization
  • 17.4 Interrupts
  • 17.5 Wait Mode
  • 17.6 I/O Signals
    • 17.6.1 TIMB Clock Pin (PTE0/TCLKB)
    • 17.6.2 TIMB Channel I/O Pins (PTE1/TCH0B-PTE2/TCH1B)
  • 17.7 I/O Registers
    • 17.7.1 TIMB Status and Control Register
    • 17.7.2 TIMB Counter Registers
    • 17.7.3 TIMB Counter Modulo Registers
    • 17.7.4 TIMB Channel Status and Control Registers
    • 17.7.5 TIMB Channel Registers
• Chapter 18 Development Support
  • 18.1 Introduction
  • 18.2 Break Module (BRK)
    • 18.2.1 Functional Description
      • 18.2.1.1 Flag Protection During Break Interrupts
      • 18.2.1.2 CPU During Break Interrupts
      • 18.2.1.3 TIM1 and TIM2 During Break Interrupts
      • 18.2.1.4 COP During Break Interrupts
    • 18.2.2 Low-Power Modes
      • 18.2.2.1 Wait Mode
      • 18.2.2.2 Stop Mode
    • 18.2.3 Break Module Registers
      • 18.2.3.1 Break Status and Control Register
      • 18.2.3.2 Break Address Registers
      • 18.2.3.3 Break Status Register
      • 18.2.3.4 TBreak Flag Control Register
  • 18.3 Monitor ROM (MON)
    • 18.3.1 Functional Description
      • 18.3.1.1 Entering Monitor Mode
      • 18.3.1.2 Normal Monitor Mode
      • 18.3.1.3 Forced Monitor Mode
      • 18.3.1.4 Data Format
      • 18.3.1.5 Echoing
      • 18.3.1.6 Break Signal
      • 18.3.1.7 Commands
      • 18.3.1.8 Baud Rate
    • 18.3.2 Security
• Chapter 19 Electrical Specifications
  • 19.1 Introduction
  • 19.2 Absolute Maximum Ratings
  • 19.3 Functional Operating Range
  • 19.4 Thermal Characteristics
  • 19.5 DC Electrical Characteristics
  • 19.6 FLASH Memory Characteristics
  • 19.7 Control Timing
  • 19.8 Serial Peripheral Interface Characteristics
  • 19.9 TImer Interface Module Characteristics
  • 19.10 Clock Generation Module Component Specifications
  • 19.11 CGM Operating Conditions
  • 19.12 CGM Acquisition/Lock Time Specifications
  • 19.13 Analog-to-Digital Converter (ADC) Characteristics
• Chapter 20 Ordering Information and Mechanical Specifications
  • 20.1 Introduction
  • 20.2 Order Numbers
  • 20.3 64-Pin Plastic Quad Flat Pack (QFP)
  • 20.4 56-Pin Shrink Dual In-Line Package (SDIP)
• Appendix A MC68HC908MR16