Freescale Semiconductor MC68HC908MR32 - Manual (Page 209)

I/O Signals
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor 209
The SPI has limited inter-integrated circuit (I
2
C) capability (requiring software support) as a master in a
single-master environment. To communicate with I
2
C peripherals, MOSI becomes an open-drain output
when the SPWOM bit in the SPI control register is set. In I
2
C communication, the MOSI and MISO pins
are connected to a bidirectional pin from the I
2
C peripheral and through a pullup resistor to V
DD
.
15.11.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin
of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI
simultaneously receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is
configured as a slave when its SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a
multiple-slave system, a logic 1 on the SS pin puts the MISO pin in a high-impedance state.
When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction
register of the shared
I/O port.
15.11.2 MOSI (Master Out/Slave In)
MOSI is one of the two SPI module pins that transmits serial data. In full-duplex operation, the MOSI pin
of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI
simultaneously transmits data from its MOSI pin and receives data on its MISO pin.
When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction
register of the shared I/O port.
15.11.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and slave devices. In a master MCU,
the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex
operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.
When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data
direction register of the shared I/O port.
15.11.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a
slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission.
See
15.5 Transmission Formats . Since it is used to indicate the start of a transmission, the SS must be
toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low
between transmissions for the CPHA = 1 format. See
Figure 15-13 .
Figure 15-13. CPHA/SS Timing
BYTE 1 BYTE 3 MISO/MOSI BYTE 2
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1