Freescale Semiconductor MC68HC908MR32 User Manual
Page 226
Timer Interface A (TIMA)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
226
Freescale Semiconductor
TOF — TIMA Overflow Flag
This read/write flag is set when the TIMA counter reaches the modulo value programmed in the TIMA
counter modulo registers. Clear TOF by reading the TIMA status and control register when TOF is set
and then writing a logic 0 to TOF. If another TIMA overflow occurs before the clearing sequence is
complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request
cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF
has no effect.
1 = TIMA counter has reached modulo value.
0 = TIMA counter has not reached modulo value.
TOIE — TIMA Overflow Interrupt Enable Bit
This read/write bit enables TIMA overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIMA overflow interrupts enabled
0 = TIMA overflow interrupts disabled
TSTOP — TIMA Stop Bit
This read/write bit stops the TIMA counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIMA counter until software clears the TSTOP bit.
1 = TIMA counter stopped
0 = TIMA counter active
NOTE
Do not set the TSTOP bit before entering wait mode if the TIMA is required
to exit wait mode. Also when the TSTOP bit is set and the timer is
configured for input capture operation, input captures are inhibited until the
TSTOP bit is cleared.
TRST — TIMA Reset Bit
Setting this write-only bit resets the TIMA counter and the TIMA prescaler. Setting TRST has no effect
on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIMA
counter is reset and always reads as logic 0. Reset clears the TRST bit.
1 = Prescaler and TIMA counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIMA counter
at a value of $0000.
Address: $000E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TOF
TOIE
TSTOP
0
0
PS2
PS1
PS0
Write:
0
TRST
R
Reset:
0
0
1
0
0
0
0
0
R
= Reserved
Figure 16-5. TIMA Status and Control Register (TASC)