Freescale Semiconductor MC68HC908MR32 User Manual

Page 248

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Timer Interface B (TIMB)

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

248

Freescale Semiconductor

MSxB — Mode Select Bit B

This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMB
channel 0.

Setting MS0B disables the channel 1 status and control register and reverts TCH1B to
general-purpose I/O.
Reset clears the MSxB bit.

1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled

MSxA — Mode Select Bit A

When ELSxB:A

≠ 00, this read/write bit selects either input capture operation or unbuffered output

compare/PWM operation. See

Table 17-2

.

1 = Unbuffered output compare/PWM operation
0 = Input capture operation

When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin once PWM, input
capture, or output compare operation is enabled. See

Table 17-2

. Reset clears the MSxA bit.

1 = Initial output level low
0 = Initial output level high

NOTE

Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIMB status and control register (TBSC).

ELSxB and ELSxA — Edge/Level Select Bits

When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.

When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.

When ELSxB and ELSxA are both clear, channel x is not connected to port E, and pin PTEx/TCHxB
is available as a general-purpose I/O pin. However, channel x is at a state determined by these bits
and becomes transparent to the respective pin when PWM, input capture, or output compare mode is
enabled.

Table 17-2

shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits.

NOTE

Before enabling a TIMB channel register for input capture operation, make
sure that the PTEx/TBCHx pin is stable for at least two bus clocks.

TOVx — Toggle-On-Overflow Bit

When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIMB counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.

1 = Channel x pin toggles on TIMB counter overflow.
0 = Channel x pin does not toggle on TIMB counter overflow.

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