Freescale Semiconductor MC68HC908MR32 - Manual (Page 52)

Analog-to-Digital Converter (ADC)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
52 Freescale Semiconductor
3.7.1 ADC Status and Control Register
This section describes the function of the ADC status and control register (ADSCR). Writing ADSCR
aborts the current conversion and initiates a new conversion.
COCO — Conversions Complete Bit
In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion.
COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit.
In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It
always reads as a 0.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled
(AIEN = 1)
NOTE
The write function of the COCO bit is reserved. When writing to the ADSCR
register, always have a 0 in the COCO bit position.
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the ADR register at the end of each
conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH[4:0] — ADC Channel Select Bits
ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field which is used to select one of 10 ADC
channels. The ADC channels are detailed in
Table 3-1 .
NOTE
Take care to prevent switching noise from corrupting the analog signal
when simultaneously using a port pin as both an analog and digital input.
The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for
reduced power consumption for the MCU when the ADC is not used.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
Address: $0040
Bit 7 6 5 4 3 2 1 Bit 0
Read: COCO
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write: R
Reset: 0 0 0 1 1 1 1 1
R = Reserved
Figure 3-4. ADC Status and Control Register (ADSCR)