Freescale Semiconductor MC68HC908MR32 - Manual (Page 72)

Clock Generator Module (CGM)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
72 Freescale Semiconductor
The K factor in the equations is derived from internal PLL parameters. K
ACQ
is the K factor when the PLL
is configured in acquisition mode, and K
TRK
is the K factor when the PLL is configured in tracking mode.
See 4.3.2.2 Acquisition and Tracking Modes .
NOTE
The inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the
reference frequency. See
4.3.2.3 Manual and Automatic PLL Bandwidth Modes A certain number of clock
cycles, n
ACQ
, is required to ascertain that the PLL is within the tracking mode entry tolerance,
∆
TRK
,
before exiting acquisition mode. A certain number of clock cycles, n
TRK
, is required to ascertain that the
PLL is within the lock mode entry tolerance,
∆
Lock
. Therefore, the acquisition time, t
ACQ
, is an integer
multiple of n
ACQ
/f
RDV
, and the acquisition to lock time, t
AL
, is an integer multiple of n
TRK
/f
RDV
. Also, since
the average frequency over the entire measurement period must be within the specified tolerance, the
total time usually is longer than t
Lock
as calculated in the previous example.
In manual mode, it is usually necessary to wait considerably longer than t
Lock
before selecting the PLL
clock (see 4.3.3 Base Clock Selector Circuit ) because the factors described in 4.8.2 Parametric
Influences on Reaction Time may slow the lock time considerably.
t
ACQ
V
DDA
f
RDV
---------------
⎝ ⎠
⎜ ⎟
⎛ ⎞
8
K
ACQ
---------------
⎝ ⎠
⎛ ⎞
=
t
AL
V
DDA
f
RDV
---------------
⎝ ⎠
⎜ ⎟
⎛ ⎞
4
K
TRK
--------------
⎝ ⎠
⎛ ⎞
=
t
Lock
t
ACQ
t
AL
+ =