Table 18-2 – Freescale Semiconductor MC68HC908MR32 User Manual
Page 258
MC6
8
HC9
08MR32
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MC6
8
HC90
8
MR16
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Semico
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Table 18-2. Monitor Mode Signal Requirements and Options
IRQ
RESET
(S1)
$FFFE
/$FFFF
PLL
PTC3 PTC4
PTC2
(S2)
External
Clock
(1)
1. External clock is derived by a 32.768 kHz crystal or a 4.9152/9.8304 MHz off-chip oscillator.
CGMOUT
Bus
Frequency
COP
For Serial
Communication
(2)
2. DNA = does not apply, X = don’t care
Comment
PTA0
PTA7
(S3)
Baud
Rate
(3)
(4)
3. PAT0 = 1 if serial communication; PTA0 = X if parallel communication
4. PTA7 = 0
→ serial, PTA7 = 1 → parallel communication for security code entry
X
GND
X
X
X
X
X
X
0
0
Disabled
X
X
0
No operation until reset goes high
V
TST
V
DD
or
V
TST
X
OFF
1
0
0
4.9152
MHz
4.9152
MHz
2.4576
MHz
Disabled
1
0
9600
PTC3 and PTC2 voltages only required if
IRQ = V
TST
; PTC2 determines frequency
divider
X
1
DNA
V
TST
V
DD
or
V
TST
X
OFF
1
0
1
9.8304
MHz
4.9152
MHz
2.4576
MHz
Disabled
1
0
9600
PTC3 and PTC2 voltages only required if
IRQ = V
TST
; PTC2 determines frequency
divider
X
1
DNA
V
DD
V
DD
$FFFF
Blank
OFF
X
X
X
9.8304
MHz
4.9152
MHz
2.4576
MHz
Disabled
1
0
9600
External frequency always divided by 4
X
1
DNA
V
DD
or
GND
V
TST
$FFFF
Blank
OFF
X
X
X
X
—
—
Enabled
X
X
—
Enters user mode — will encounter an
illegal address reset
V
DD
or
GND
V
DD
or
V
TST
Non-$FF
Programmed
OFF
X
X
X
X
—
—
Enabled
X
X
—
Enters user mode