Freescale Semiconductor MC68HC908MR32 - Manual (Page 192)

System Integration Module (SIM)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
192 Freescale Semiconductor
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
14.7.2 SIM Reset Status Register
The SIM reset status register (SRSR) contains six flags that show the source of the last reset. Clear the
SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the
register.
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
MENRST — Forced Monitor Mode Entry Reset Bit
1 = Last reset caused by the MENRST circuit
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by the LVI circuit
0 = POR or read of SRSR
Address: $FE01
BIt 7 6 5 4 3 2 1 Bit 0
Read: POR PIN COP ILOP ILAD MENRST LVI 0
Write: R R R R R R R R
Reset: 1 0 0 0 0 0 0 0
R = Reserved
Figure 14-15. SIM Reset Status Register (SRSR)