Freescale Semiconductor MC68HC908MR32 User Manual

Page 32

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Memory

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

32

Freescale Semiconductor

$0032

PWM 5 Value Register High

(PMVAL5H)

See page 145.

Read:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Write:

Reset:

0

0

0

0

0

0

0

0

$0033

PWM 5 Value Register Low

(PVAL5L)

See page 145.

Read:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Write:

Reset:

0

0

0

0

0

0

0

0

$0034

PWM 6 Value Register High

(PVAL6H)

See page 145.

Read:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Write:

Reset:

0

0

0

0

0

0

0

0

$0035

PWM 6 Value Register Low

(PMVAL6L)

See page 145.

Read:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Write:

Reset:

0

0

0

0

0

0

0

0

$0036

Dead-Time Write-Once

Register (DEADTM)

See page 150.

Read:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Write:

Reset:

1

1

1

1

1

1

1

1

$0037

PWM Disable Mapping

Write-Once Register (DISMAP)

See page 137.

Read:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Write:

Reset:

1

1

1

1

1

1

1

1

$0038

SCI Control Register 1

(SCC1)

See page 169.

Read:

LOOPS

ENSCI

TXINV

M

WAKE

ILTY

PEN

PTY

Write:

Reset:

0

0

0

0

0

0

0

0

$0039

SCI Control Register 2

(SCC2)

See page 171.

Read:

SCTIE

TCIE

SCRIE

ILIE

TE

RE

RWU

SBK

Write:

Reset:

0

0

0

0

0

0

0

0

$003A

SCI Control Register 3

(SCC3)

See page 173.

Read:

R8

T8

0

0

ORIE

NEIE

FEIE

PEIE

Write:

R

R

R

Reset:

U

U

0

0

0

0

0

0

$003B

SCI Status Register 1

(SCS1)

See page 174.

Read:

SCTE

TC

SCRF

IDLE

OR

NF

FE

PE

Write:

R

R

R

R

R

R

R

R

Reset:

1

1

0

0

0

0

0

0

$003C

SCI Status Register 2

(SCS2)

See page 176.

Read:

0

0

0

0

0

0

BKF

RPF

Write:

R

R

R

R

R

R

R

R

Reset:

0

0

0

0

0

0

0

0

$003D

SCI Data Register

(SCDR)

See page 177.

Read:

R7

R6

R5

R4

R3

R2

R1

R0

Write:

T7

T6

T5

T4

T3

T2

T1

T0

Reset:

Unaffected by reset

Addr.

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

U = Unaffected

X = Indeterminate

R

= Reserved

Bold

= Buffered

= Unimplemented

Figure 2-2. Control, Status, and Data Registers Summary (Sheet 5 of 8)

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