Freescale Semiconductor MC68HC908MR32 - Manual (Page 149)

Control Logic Block
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor 149
NOTE
When reading this bit, the value read is the buffer value (not necessarily the
value the output control block is currently using).
The IPOLx bits take effect at the beginning of the next load cycle,
regardless of the state of the load okay bit, LDOK.
IPOL2 — Top/Bottom Correction Bit for PWM Pair 2 (PWMs 3 and 4)
This buffered read/write bit selects which PWM value register is used if top/bottom correction is to be
achieved without current sensing.
1 = Use PWM value register 4.
0 = Use PWM value register 3.
NOTE
When reading this bit, the value read is the buffer value (not necessarily the
value the output control block is currently using).
IPOL3 — Top/Bottom Correction Bit for PWM Pair 3 (PWMs 5 and 6)
This buffered read/write bit selects which PWM value register is used if top/bottom correction is to be
achieved without current sensing.
1 = Use PWM value register 6.
0 = Use PWM value register 5.
NOTE
When reading this bit, the value read is the buffer value (not necessarily the
value the output control block is currently using).
PRSC1 and PRSC0 — PWM Prescaler Bits
These buffered read/write bits allow the PWM clock frequency to be modified as shown in Table 12-9 .
NOTE
When reading these bits, the value read is the buffer value (not necessarily
the value the PWM generator is currently using).
Table 12-9. PWM Prescaler
Prescaler Bits
PRSC1 and PRSC0
PWM Clock Frequency
00 f
OP
01 f
OP
/2
10 f
OP
/4
11 f
OP
/8