Freescale Semiconductor MC68HC908MR32 - Manual (Page 95)

IRQ Status and Control Register
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor 95
IMASK1 — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK1.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE1 — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE1.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
IRQF — IRQ Flag
This read-only bit acts as a status flag, indicating an IRQ event occurred.
1 = External IRQ event occurred.
0 = External IRQ event did not occur.