Freescale Semiconductor MC68HC908MR32 - Manual (Page 74)

Configuration Register (CONFIG)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
74 Freescale Semiconductor
5.3 Configuration Register
EDGE — Edge-Align Enable Bit
EDGE determines if the motor control PWM will operate in edge-aligned mode or center-aligned mode.
See
Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC) .
1 = Edge-aligned mode enabled
0 = Center-aligned mode enabled
BOTNEG — Bottom-Side PWM Polarity Bit
BOTNEG determines if the bottom-side PWMs will have positive or negative polarity. See Chapter 12
Pulse-Width Modulator for Motor Control (PWMMC) .
1 = Negative polarity
0 = Positive polarity
TOPNEG — Top-Side PWM Polarity Bit
TOPNEG determines if the top-side PWMs will have positive or negative polarity. See Chapter 12
Pulse-Width Modulator for Motor Control (PWMMC) .
1 = Negative polarity
0 = Positive polarity
INDEP — Independent Mode Enable Bit
INDEP determines if the motor control PWMs will be six independent PWMs or three complementary
PWM pairs. See
Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC) .
1 = Six independent PWMs
0 = Three complementary PWM pairs
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. See
Chapter 9 Low-Voltage Inhibit (LVI) .
1 = LVI module resets enabled
0 = LVI module resets disabled
LVIPWR — LVI Power Enable Bit
LVIPWR enables the LVI module. Chapter 9 Low-Voltage Inhibit (LVI)
1 = LVI module power enabled
0 = LVI module power disabled
STOPE — Stop Enable Bit
Writing a 0 or a 1 to bit 1 has no effect on MCU operation. Bit 1 operates the same as the other bits
within this write-once register operate.
1 = STOP mode enabled
0 = STOP mode disabled
COPD — COP Disable Bit
COPD disables the COP module. See Chapter 6 Computer Operating Properly (COP) .
1 = COP module disabled
0 = COP module enabled
Address: $001F
Bit 7 6 5 4 3 2 1 Bit 0
Read:
EDGE BOTNEG TOPNEG INDEP LVIRST LVIPWR STOPE COPD
Write:
Reset: 0 0 0 0 1 1 0 0
Figure 5-1. Configuration Register (CONFIG)