2 tima counter registers, Tima counter registers – Freescale Semiconductor MC68HC908MR32 User Manual
Page 227
I/O Registers
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
227
PS[2:0] — Prescaler Select Bits
These read/write bits select either the
PTE3/TCLKA
pin or one of the seven prescaler outputs as the
input to the TIMA counter as
shows. Reset clears the PS[2:0] bits.
16.7.2 TIMA Counter Registers
The two read-only TIMA counter registers contain the high and low bytes of the value in the TIMA counter.
Reading the high byte (TACNTH) latches the contents of the low byte (TACNTL) into a buffer. Subsequent
reads of TACNTH do not affect the latched TACNTL value until TACNTL is read. Reset clears the TIMA
counter registers. Setting the TIMA reset bit (TRST) also clears the TIMA counter registers.
NOTE
If TACNTH is read during a break interrupt, be sure to unlatch TACNTL by
reading TACNTL before exiting the break interrupt. Otherwise, TACNTL
retains the value latched during the break.
Table 16-1. Prescaler Selection
PS[2:0]
TIMA Clock Source
000
Internal bus clock
÷1
001
Internal bus clock
÷ 2
010
Internal bus clock
÷ 4
011
Internal bus clock
÷ 8
100
Internal bus clock
÷ 16
101
Internal bus clock
÷ 32
110
Internal bus clock
÷ 64
111
PTE3/TCLKA
Register Name and Address:
TACNTH — $000F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
Register Name and Address:
TACNTL — $0010
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 16-6. TIMA Counter Registers (TACNTH and TACNTL)