2 timb counter registers, 3 timb counter modulo registers, Timb counter registers – Freescale Semiconductor MC68HC908MR32 User Manual
Page 246: Timb counter modulo registers
Timer Interface B (TIMB)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
246
Freescale Semiconductor
17.7.2 TIMB Counter Registers
The two read-only TIMB counter registers contain the high and low bytes of the value in the TIMB counter.
Reading the high byte (TBCNTH) latches the contents of the low byte (TBCNTL) into a buffer. Subsequent
reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL is read. Reset clears the TIMB
counter registers. Setting the TIMB reset bit (TRST) also clears the TIMB counter registers.
NOTE
If TBCNTH is read during a break interrupt, be sure to unlatch TBCNTL by
reading TBCNTL before exiting the break interrupt. Otherwise, TBCNTL
retains the value latched during the break.
17.7.3 TIMB Counter Modulo Registers
The read/write TIMB modulo registers contain the modulo value for the TIMB counter. When the TIMB
counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIMB counter resumes
counting from $0000 at the next timer clock. Writing to the high byte (TBMODH) inhibits the TOF bit and
overflow interrupts until the low byte (TBMODL) is written. Reset sets the TIMB counter modulo registers.
NOTE
Reset the TIMB counter before writing to the TIMB counter modulo registers.
Register Name and Address:
TBCNTH — $0052
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
Register Name and Address:
TBCNTL — $0053
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 17-6. TIMB Counter Registers (TBCNTH and TBCNTL)
Register Name and Address:
TBMODH — $0054
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
1
1
1
1
1
1
1
1
Register Name and Address:
TBMODL — $0055
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
1
1
1
1
1
1
1
1
Figure 17-7. TIMB Counter Modulo Registers (TBMODH and TBMODL)