9 fault status register, Fault status register – Freescale Semiconductor MC68HC908MR32 User Manual
Page 152
Pulse-Width Modulator for Motor Control (PWMMC)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
152
Freescale Semiconductor
12.9.9 Fault Status Register
The fault status register (FSR) is a read-only register that indicates the current fault status.
FPIN4 — State of Fault Pin 4 Bit
This read-only bit allows the user to read the current state of fault
pin 4.
1 = Fault pin 4 is at logic 1.
0 = Fault pin 4 is at logic 0.
FFLAG4 — Fault Event Flag 4
The FFLAG4 event bit is set within two CPU cycles after a rising edge on fault pin 4. To clear the
FFLAG4 bit, the user must write a 1 to the FTACK4 bit in the fault acknowledge register.
1 = A fault has occurred on fault pin 4.
0 = No new fault on fault pin 4
FPIN3 — State of Fault Pin 3 Bit
This read-only bit allows the user to read the current state of fault
pin 3.
1 = Fault pin 3 is at logic 1.
0 = Fault pin 3 is at logic 0.
FFLAG3 — Fault Event Flag 3
The FFLAG3 event bit is set within two CPU cycles after a rising edge on fault pin 3. To clear the
FFLAG3 bit, the user must write a 1 to the FTACK3 bit in the fault acknowledge register.
1 = A fault has occurred on fault pin 3.
0 = No new fault on fault pin 3.
FPIN2 — State of Fault Pin 2 Bit
This read-only bit allows the user to read the current state of fault pin 2.
1 = Fault pin 2 is at logic 1.
0 = Fault pin 2 is at logic 0.
FFLAG2 — Fault Event Flag 2
The FFLAG2 event bit is set within two CPU cycles after a rising edge on fault pin 2. To clear the
FFLAG2 bit, the user must write a 1 to the FTACK2 bit in the fault acknowledge register.
1 = A fault has occurred on fault pin 2.
0 = No new fault on fault pin 2
FPIN1 — State of Fault Pin 1 Bit
This read-only bit allows the user to read the current state of fault pin 1.
1 = Fault pin 1 is at logic 1.
0 = Fault pin 1 is at logic 0.
Address:
$0023
Bit 7
6
5
4
3
2
1
Bit 0
Read:
FPIN4
FFLAG4
FPIN3
FFLAG3
FPIN2
FFLAG2
FPIN1
FFLAG1
Write:
Reset:
U
0
U
0
U
0
U
0
= Unimplemented
U = Unaffected
Figure 12-44. Fault Status Register (FSR)