Freescale Semiconductor MC68HC908MR32 - Manual (Page 104)

Input/Output (I/O) Ports (PORTS)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
104 Freescale Semiconductor
Figure 10-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a
logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Table 10-1 summarizes the operation of the port A pins.
10.3 Port B
Port B is an 8-bit, general-purpose, bidirectional I/O port that shares its pins with the analog-to-digital
convertor (ADC) module.
10.3.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight port B pins.
PTB[7:0] — Port B Data Bits
These read/write bits are software-programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
Table 10-1. Port A Pin Functions
DDRA Bit PTA Bit I/O Pin Mode
Accesses to DDRA Accesses to PTA
Read/Write Read Write
0 X
(1)
1. X = don’t care
Input, Hi-Z
(2)
2. Hi-Z = high impedance
DDRA[7:0] Pin PTA[7:0]
(3)
3. Writing affects data register, but does not affect input.
1 X Output DDRA[7:0] PTA[7:0] PTA[7:0]
Address: $0001
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Write:
Reset: Unaffected by reset
Figure 10-5. Port B Data Register (PTB)
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
READ PTA ($0000)
PTAx
DDRAx
PTAx
INT
ERNAL DATA BUS