Freescale Semiconductor MC68HC908MR32 - Manual (Page 139)

Fault Protection
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor 139
Figure 12-27. PWM Disabling Decode Scheme
12.6.1.1 Fault Pin Filter
Each fault pin incorporates a filter to assist in determining a genuine fault condition. After a fault pin has
been logic low for one CPU cycle, a rising edge (logic high) will be synchronously sampled once per CPU
cycle for two cycles. If both samples are detected logic high, the corresponding FPIN bit and FFLAG bit
will be set. The FPIN bit will remain set until the corresponding fault pin is logic low and synchronously
sampled once in the following CPU cycle.
12.6.1.2 Automatic Mode
In automatic mode, the PWM(s) are disabled immediately once a filtered fault condition is detected (logic
high). The PWM(s) remain disabled until the filtered fault condition is cleared (logic low) and a new PWM
cycle begins as shown in
Figure 12-28 . Clearing the corresponding FFLAGx event bit will not enable the
PWMs in automatic mode.
The filtered fault pin’s logic state is reflected in the respective FPINx bit. Any write to this bit is overwritten
by the pin state. The FFLAGx event bit is set with each rising edge of the respective fault pin after filtering
has been applied. To clear the FFLAGx bit, the user must write a 1 to the corresponding FTACKx bit.
f the FINTx bit is set, a fault condition resulting in setting the corresponding FFLAG bit will also latch a
CPU interrupt request. The interrupt request latch is not cleared until one of these actions occurs:
• The FFLAGx bit is cleared by writing a 1 to the corresponding FTACKx bit.
• The FINTx bit is cleared. This will not clear the FFLAGx bit.
• A reset automatically clears all four interrupt latches.
BIT 7
BIT 3
BIT 0
BIT 1
BIT 2
BIT 4
BIT 5
BIT 6
BANK X
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
BANK Y
PWM PIN 1
PWM PIN 2
PWM PIN 3
PWM PIN 4
PWM PIN 5
PWM PIN 6