Freescale Semiconductor MC68HC908MR32 - Manual (Page 269)

Serial Peripheral Interface Characteristics
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor 269
19.8 Serial Peripheral Interface Characteristics
Diagram
Number
(1)
1. V
DD
= 5.0 Vdc ± 10%, all timing is shown with respect to 20% V
DD
and 70% V
DD
, unless otherwise noted; assumes 100 pF
load on all SPI pins
Characteristic (2)
2. Numbers refer to dimensions in Figure 19-1 and Figure 19-2 .
Symbol Min Max Unit
Operating frequency
Master
Slave f
OP(M)
f
OP(S)
f
OP
/128
dc
f
OP
/2
f
OP
MHz
1
Cycle time
Master
Slave t
CYC(M)
t
CYC(S)
2
1 128
—
t
CYC
2 Enable lead time t
Lead(S)
15 — ns
3 Enable lag time t
Lag(S)
15 — ns
4
Clock (SPCK) high time
Master
Slave t
SCKH(M)
t
SCKH(S)
100
50
—
— ns
5
Clock (SPCK) low time
Master
Slave t
SCKL(M)
t
SCKL(S)
100
50
—
— ns
6
Data setup time (inputs)
Master
Slave
t
SU(M)
t
SU(S)
45
5
—
—
ns
7
Data hold time (inputs)
Master
Slave
t
H(M)
t
H(S)
0
15
—
—
ns
8
Access time, slave (3)
CPHA = 0
CHPA = 1
3. Time to data active from high-impedance state
t
A(CP0)
t
A(CP1)
0
0 40
20
ns
9 Disable time, slave
(4)
4. Hold time to high-impedance state
t
DIS(S)
— 25 ns
10
Data valid time after enable edge
Master
Slave (5)
5. With 100 pF on all SPI pins
t
V(M)
t
V(S)
—
— 10
40 ns