Figure411 hi register map, 3 interrupt control register (icr), 1 icr receive request enable (rreq)—bit 0 – Motorola DSP56012 User Manual

Page 104: 2 icr transmit request enable (treq)—bit 1, Interrupt control register (icr) -24, Icr receive request enable (rreq)—bit 0 -24, Icr transmit request enable (treq)—bit 1 -24, Figure 4-11, Hi register map -24

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Figure411 hi register map, 3 interrupt control register (icr), 1 icr receive request enable (rreq)—bit 0 | 2 icr transmit request enable (treq)—bit 1, Interrupt control register (icr) -24, Icr receive request enable (rreq)—bit 0 -24, Icr transmit request enable (treq)—bit 1 -24, Figure 4-11, Hi register map -24 | Motorola DSP56012 User Manual | Page 104 / 270 Figure411 hi register map, 3 interrupt control register (icr), 1 icr receive request enable (rreq)—bit 0 | 2 icr transmit request enable (treq)—bit 1, Interrupt control register (icr) -24, Icr receive request enable (rreq)—bit 0 -24, Icr transmit request enable (treq)—bit 1 -24, Figure 4-11, Hi register map -24 | Motorola DSP56012 User Manual | Page 104 / 270
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