Motorola DSP56012 - Manual (Page 63)

Memory, Operating Modes, and Interrupts
Introduction
MOTOROLA DSP56012 User’s Manual 3-3
3.1 INTRODUCTION
The DSP56012 program and data memories are independent, and the on-chip data
memory is divided into two separate memory spaces, X and Y. There are also two
on-chip data ROMs in the X and Y data memory spaces, and a bootstrap ROM that
can overlay part of the Program RAM. The data memories are divided into two
independent spaces to work with the two Address ALUs to feed two operands
simultaneously to the Data ALU. Through the use of Program RAM Enable bits (PEA
and PEB) in the Operating Mode Register (OMR), four different memory
configurations are possible to provide appropriate memory sizes for a variety of
applications (see
Table 3-1 ).
This section also includes details of the interrupt vectors and priorities and describes
the effect of a hardware reset on the PLL Multiplication Factor (MF).
3.2 DSP56012 DATA AND PROGRAM MEMORY
The memory in the DSP56012 can be mapped into four different configurations
according to the PEA and PEB bits of the OMR register. The internal data and
program memory configurations are shown in
Table 3-1 .
Note: Internal Data and Program ROMs are factory-programmed to support
specific applications. Refer to the
DSP56012 Technical Data sheet,
order number DSP56012/D, for more information about available
configurations.
Table 3-1 Internal Memory Configurations
Memory Type
No Switch
(PEA = 0,
PEB = 0)
Switch A
(PEA = 1,
PEB = 0)
Switch B
(PEA = 0,
PEB = 1)
Switch A + B
(PEA = 1,
PEB = 1)
Program RAM 0.25 K 1.0 K 1.75 K 2.5 K
XRAM 4.0 K 3.25 K 3.25 K 2.5 K
YRAM 4.25 K 4.25 K 3.5 K 3.5 K
Program ROM 15 K 15 K 15 K 15 K
XROM 3.5 K 3.5 K 3.5 K 3.5 K
YROM 2.0 K 2.0 K 2.0 K 2.0 K