Motorola DSP56012 - Manual (Page 145)

Parallel Host Interface
Host Interface (HI)
MOTOROLA DSP56012 User’s Manual 4-65
4.4.8.3.4 DSP to Host—DMA Procedure
The following procedure outlines the typical steps that the host processor must take
to setup and terminate a DSP-to-host DMA transfer.
1. Set up the DMA controller (1) destination address, byte count, direction, and
other control registers. Enable the DMA controller channel.
2. Initialize the HI (2) by writing the ICR to select the word size (HM0 and HM1),
the direction (TREQ = 0, RREQ = 1), and setting INIT = 1.
3. The DSP’s source pointer (3) used in the DMA interrupt handler (e.g., an
address register) must be initialized, and HTIE must be set to enable the DSP
host transmit interrupt. This could be done by the host processor with a host
command interrupt routine.
4. The DSP host transmit interrupt will be activated immediately after HTIE is
set. The DSP CPU will move data to HOTX. The HI circuitry will transfer the
contents of HOTX to RXH:RXM:RXL, setting RXDF, which asserts HOREQ.
Asserting HOREQ (4) starts the DMA transfer from RXH, RXM, and RXL to
the host processor.
5. Perform other tasks (5) while the DMA controller transfers data (6) until
interrupted by the DMA controller DMA complete interrupt (7). The DSP
Interrupt Control Register (ICR), the Interrupt Status Register (ISR), and TXH,
TXM, and TXL can be accessed at any time by the host processor but the RXH,
RXM and RXL registers can not be accessed until the DMA mode is disabled.
6. Terminate the DMA controller channel (8) to disable DMA transfers.
7. Terminate the DSP Host DMA mode (9) in the Interrupt Control Register
(ICR) by clearing bits HM1 and HM0 and clearing RREQ.
4.4.8.4 HI Port Usage Considerations—Host Side
Synchronization is a common problem when two asynchronous systems are
connected, and careful synchronization is required when reading multi-bit registers
that are written by another asynchronous system. The considerations for proper
operation are discussed below.
4.4.8.4.1 Unsynchronized Reading of Receive Byte Registers
When reading receive byte registers, RXH, RXM, or RXL, the host programmer
should use interrupts or poll the RXDF flag which indicates that data is available.
This guarantees that the data in the receive byte registers will be stable.