Motorola DSP56012 - Manual (Page 76)

3-16 DSP56012 User’s Manual MOTOROLA
Memory, Operating Modes, and Interrupts
Interrupt Priority Register
Figure 3-6 Interrupt Priority Register (Addr X:$FFFF)
Table 3-4 Interrupt Priorities
Priority Interrupt
Level 3 (Nonmaskable)
Highest
Lowest
Hardware RESET
Illegal Instruction
NMI
Stack Error
Trace
SWI
Levels 0, 1, 2 (Maskable)
Highest IRQA
IRQB
SAI Receiver Exception
SAI Transmitter Exception
SAI Left Channel Receiver
SAI Left Channel Transmitter
IAL1 IAL0 IAL2 IBL0 IBL1 IBL2 SAL0 SAL1
0 11 10 9 8 7 6 5 4 3 2 1
Reserved, read as 0, and should be written with 0 for future compatibility
SHL1 SHL0 HPL0 HPL1
12 23 22 21 20 19 18 17 16 15 14 13
IRQA Mode
IRQB Mode
Reserved
SAI IPL
SHI IPL
Host IPL
Reserved
AA0292.11
DTL1 DTL0
DAX IPL