Motorola DSP56012 - Manual (Page 31)

Overview
DSP56012 Architectural Overview
MOTOROLA DSP56012 User’s Manual 1-11
1.3.2.1 Data Arithmetic and Logic Unit (Data ALU)
The Data Arithmetic and Logic Unit (Data ALU) has been designed to be fast and
provide the capability to process signals having a wide dynamic range. Special
circuitry has been provided to facilitate the processing of data overflows and
round-off errors. The Data ALU performs all of the arithmetic and logical
operations on data operands. The Data ALU consists of four 24-bit input registers,
two 48-bit accumulator registers (also usable as four 24-bit accumulators), two 8-bit
accumulator extension registers, an accumulator shifter, two data shifter/limiters,
and a parallel single-cycle non-pipelined Multiplier-Accumulator (MAC). Data
ALU operations use fractional two’s-complement arithmetic. Data ALU registers
may be read or written over the X Data Bus (XDB) and Y Data Bus (YDB) as 24- or
48-bit operands. The 24-bit data words provide 144 dB of dynamic range. This is
sufficient for most real-world applications, including high-quality audio
applications, since the majority of Analog-to-Digital (A/D) and Digital-to-Analog
(D/A) converters are 16 bits or less, and certainly not greater than 24 bits. The 56-bit
accumulation internal to the Data ALU provides 336 dB of internal dynamic range,
assuring no loss of precision due to intermediate processing.
Two data shifter/limiters provide special post-processing on data reads (from the
Data ALU accumulator registers and directed to the XDB or YDB). The data shifters
are capable of shifting data one bit to the left or to the right, as well as passing the
data unshifted. Each data shifter has a 24-bit output with overflow indication. The
data shifters are controlled by scaling-mode bits. These shifters permit no-overhead
dynamic scaling of fixed point data by simply programming the scaling mode bits.
This permits block floating-point algorithms to be implemented efficiently. For
example, Fast Fourier Transform (FFT) routines can use this feature to selectively
scale each butterfly pass. Saturation arithmetic is accommodated to minimize errors
due to overflow. Overflow occurs when a source operand requires more bits for
accurate representation than there are available in the destination. To minimize the
error due to overflow, “limiting” causes the maximum (or minimum, if negative)
value to be written to the destination with an error flag.
1.3.2.2 Address Generation Unit (AGU)
The Address Generation Unit (AGU) performs all address storage and effective
address calculations necessary to access data operands in memory. It implements
three types of arithmetic to update addresses—linear, modulo, and reverse carry.
This unit operates in parallel with other chip resources to minimize address
generation overhead. The AGU contains eight address registers R[7:0] (i.e., Rn), eight
offset registers N[7:0] (i.e., Nn), and eight modifier registers M[7:0] (i.e., Mn). The Rn
are 16-bit registers that may contain an address or data. Each Rn register may
provide addresses to the X memory Address Bus (XAB), Y memory Address Bus
(YAB), and the Program Address Bus (PAB). The Nn and Mn registers are 16-bit
registers that are normally used to update the Rn registers, but may be used for data.