Motorola DSP56012 - Manual (Page 9)

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6.3.2.10 RCS Receiver Data Word Truncation (RDWT)—Bit 106-14
6.3.2.11 RCS Receiver Interrupt Enable (RXIE)—Bit 11 . . . . . 6-15
6.3.2.12 RCS Receiver Interrupt Location (RXIL)—Bit 12 . . . . 6-15
6.3.2.13 RCS Receiver Left Data Full (RLDF)—Bit 14 . . . . . . 6-16
6.3.2.14 RCS Receiver Right Data Full (RRDF)—Bit 15 . . . . . 6-16
6.3.3 SAI Receive Data Registers (RX0 and RX1) . . . . . . . . . 6-17
6.3.4 Transmitter Control/Status Register (TCS). . . . . . . . . . . 6-17
6.3.4.1 TCS Transmitter 0 Enable (T0EN)—Bit 0 . . . . . . . . . 6-17
6.3.4.2 TCS Transmitter 1 Enable (T1EN)—Bit 1 . . . . . . . . . 6-17
6.3.4.3 TCS Transmitter 2 Enable (T2EN)—Bit 2 . . . . . . . . . 6-18
6.3.4.4 TCS Transmitter Master (TMST)—Bit 3. . . . . . . . . . . 6-18
6.3.4.5 TCS Transmitter Word Length Control (TWL[1:0])—Bits 4 & 5
6-18
6.3.4.6 TCS Transmitter Data Shift Direction (TDIR)—Bit 6 . 6-18
6.3.4.7 TCS Transmitter Left Right Selection (TLRS)—Bit 7 . 6-19
6.3.4.8 TCS Transmitter Clock Polarity (TCKP)—Bit 8 . . . . . 6-19
6.3.4.9 TCS Transmitter Relative Timing (TREL)—Bit 9 . . . . 6-20
6.3.4.10 TCS Transmitter Data Word Expansion (TDWE)—Bit 106-20
6.3.4.11 TCS Transmitter Interrupt Enable (TXIE)—Bit 11 . . . 6-21
6.3.4.12 TCS Transmitter Interrupt Location (TXIL)—Bit 12 . . 6-22
6.3.4.13 TCS Reserved Bit—Bit 13 . . . . . . . . . . . . . . . . . . . . . 6-22
6.3.4.14 TCS Transmitter Left Data Empty (TLDE)—Bit 14 . . 6-22
6.3.4.15 TCS Transmitter Right Data Empty (TRDE)—Bit 15 . 6-23
6.3.5 SAI Transmit Data Registers (TX2, TX1 and TX0). . . . . 6-23
6.4 PROGRAMMING CONSIDERATIONS. . . . . . . . . . . . . . . . 6-24
6.4.1 SAI Operation During Stop . . . . . . . . . . . . . . . . . . . . . . . 6-24
6.4.2 Initiating a Transmit Session . . . . . . . . . . . . . . . . . . . . . 6-24
6.4.3 Using a Single Interrupt to Service Both Receiver and
Transmitter Sections6-24
6.4.4 SAI State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
7.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.2 GPIO PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . 7-3
7.3 GPIO REGISTER (GPIOR). . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.3.1 GPIOR Data Bits (GD[7:0])—Bits 7–0 . . . . . . . . . . . . . . . 7-4
7.3.2 GPIOR Data Direction Bits (GDD[7:0])—Bits 15–8 . . . . . 7-4
7.3.3 GPIOR Control Bits (GC[7:0])—Bits 23–16 . . . . . . . . . . . 7-4
8.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.2 DAX SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4