Motorola DSP56012 User Manual
Page 269
Motorola
I-5
Programming Model
RCS
Receiver 0 Enable
Receiver 1 Enable
Receiver Clock Polarity
Receiver Data Shift Direction
Receiver Data Word Truncation
Receiver Interrupt Enable
Receiver Interrupt Location
Receiver Left Data Full
Receiver Left Right Selection
Receiver Master
Receiver Relative Timing
Receiver Right Data Full
Receiver Word Length Control
Receive Data Registers
Receive Section
Receive Section Block Diagram
Receiver Clock Polarity (RCKP)
Programming
Receiver Clock Polarity Programming
Receiver Control/Status Register
Receiver Data Shift Direction (RDIR)
Programming
Receiver Data Word Truncation (RDWT)
Programming
Receiver Left Right Selection (RLRS)
Programming
Receiver Relative Timing (RREL)
Programming
Registers
Single Interrupt To Service Receiver And
Transmitter
TCS
Transmitter 0 Enable
Transmitter 1 Enable
Transmitter 2 Enable
Transmitter Clock Polarity
Transmitter Data Shift Direction
Transmitter Data Word Expansion
Transmitter Interrupt Enable
Transmitter Interrupt Location
Transmitter Left Data Empty
Transmitter Left Right Selection
Transmitter Master
Transmitter Relative Timing
Transmitter Right Data Empty
Transmitter Word Length Control
Transmit Data Registers
Transmit Section
Transmit Section Block Diagram
Transmitter Clock Polarity Programming
Transmitter Control/Status Register
(TCS)
Transmitter Data Shift Direction
Programming
Transmitter Data Word Expansion
Programming
Transmitter Left Right Selection
Programming
Serial Audio Interface — See Section 6
Serial Audio Interface (SAI)
Serial Host Interface (SHI)
Serial Host Interface—See Section 5
Serial Peripheral Interface Bus
SHI
Block Diagram
Clock Control Register—DSP Side
Clock Generator
Control/Status Register—DSP Side
Data Size
Exception Priorities
HCKR
Clock Phase and Polarity Controls
Divider Modulus Select
Prescaler Rate Select
HCKR Filter Mode
HCSR
Bus Error Interrupt Enable
FIFO Enable Control
Host Request Enable
Idle
Master Mode
Serial Host Interface I
2
C/SPI
Selection
Serial Host Interface Mode
SHI Enable
Host Receive Data FIFO—DSP Side
Host Transmit Data Register—DSP Side
HREQ
Function In SHI Slave Modes
HSAR
I
2
C Slave Address
Slave Address Register
I/O Shift Register
Input/Output Shift Register—Host Side
Internal Architecture
Internal Interrupt Priorities
Interrupt Vectors
Introduction
Operation During Stop
Programming Considerations
Programming Model
Programming Model—DSP Side
Programming Model—Host Side
Slave Address Register—DSP Side
SHI Noise Reduction Filter Mode
SPI