Motorola DSP56012 - Manual (Page 166)

5-18 DSP56012 User’s Manual MOTOROLA
Serial Host Interface
Serial Host Interface Programming Model
CPHA = 0, HTDE is set after the end of the data word transmission. HTDE is cleared
when HTX is written by the DSP. HTDE is set by hardware reset, software reset, SHI
individual reset, and during the Stop state.
5.4.6.14 Host Receive FIFO Not Empty (HRNE)—Bit 17
The read-only status bit Host Receive FIFO Not Empty (HRNE) indicates that the
Host Receive FIFO (HRX) contains at least one data word. HRNE is set when the
FIFO is not empty. HRNE is cleared when HRX is read by the DSP, reducing the
number of words in the FIFO to 0. HRNE is cleared during hardware reset, software
reset, SHI individual reset, and during the Stop state.
5.4.6.15 Host Receive FIFO Full (HRFF)—Bit 19
The read-only status bit Host Receive FIFO Full (HRFF) indicates that the Host
Receive FIFO (HRX) is full. HRFF is set when the HRX FIFO is full. HRFF is cleared
when HRX is read by the DSP and at least one place is available in the FIFO. HRFF is
cleared by hardware reset, software reset, SHI individual reset, and during the Stop
state.
5.4.6.16 Host Receive Overrun Error (HROE)—Bit 20
The read-only status bit Host Receive Overrun Error (HROE) indicates that a
data-receive overrun error occurred. Receive-overrun errors can not occur when
operating in the I
2
C Master mode, since the clock is suspended if the receive FIFO is
full. HROE is set when the shift register (IOSR) is filled and ready to transfer the data
word to the HRX FIFO and the FIFO is already full (HRFF is set). When a
receive-overrun error occurs, the shift register is not transferred to the FIFO. If a
receive interrupt occurs with HROE set, the receive-overrun interrupt vector will be
generated. If a receive interrupt occurs with HROE cleared, the regular receive-data
interrupt vector will be generated. HROE is cleared by reading the HCSR with HROE
set, followed by reading HRX. HROE is cleared by hardware reset, software reset,
SHI individual reset, and during the Stop state.
5.4.6.17 Host Bus Error (HBER)—Bit 21
The read-only status bit Host Bus Error (HBER) indicates that an SHI bus error
occurred when operating as a master (HMST set). In I
2
C mode, HBER is set if the
transmitter does not receive an acknowledge after a byte is transferred; in this case, a
stop event will be generated and then transmission will be suspended. In SPI mode,
the bit is set if SS is asserted; in this case, transmission is suspended at the end of
transmission of the current word. HBER is cleared only by hardware reset, software
reset, SHI individual reset, and during the Stop state.