Motorola DSP56012 - Manual (Page 163)

Serial Host Interface
Serial Host Interface Programming Model
MOTOROLA DSP56012 User’s Manual 5-15
recommended that an SHI individual reset be generated (HEN cleared) before
changing HMST. HMST is cleared during hardware reset and software reset.
5.4.6.7 HCSR Host-Request Enable (HRQE[1:0])—Bits 8–7
The read/write Host-Request Enable control bits (HRQE[1:0]) are used to enable the
operation of the HREQ pin. When HRQE[1:0] are cleared, the HREQ pin is disabled
and held in the high impedance state. If either HRQE0 or HRQE1 are set and the SHI
is operating in a Master mode, the HREQ pin becomes an input that controls SCK:
deasserting HREQ will suspend SCK. If either HRQE0 or HRQE1 are set and the SHI
is operating in a Slave mode, HREQ becomes an output and its operation is defined
in
Table 5-5 . HRQE[1:0] should be modified only when the SHI is idle (HBUSY = 0).
HRQE[1:0] are cleared during hardware reset and software reset.
5.4.6.8 HCSR Idle (HIDLE)—Bit 9
The read/write control/status bit Host Idle (HIDLE) is used only in the I
2
C Master
mode; it is ignored otherwise. It is only possible to set the HIDLE bit during writes to
the HCSR. HIDLE is cleared by writing to HTX. To ensure correct transmission of the
slave device address byte, HIDLE should be set only when HTX is empty (HTDE =
1). After HIDLE is set, a write to HTX will clear HIDLE and cause the generation of a
stop event, a start event, and then the transmission of the eight MSBs of the data as
the slave device address byte. While HIDLE is cleared, data written to HTX will be
transmitted ‘as is.’ If the SHI completes transmitting a word and there is no new data
in HTX, the clock will be suspended after sampling ACK.
HIDLE determines the acknowledge that the receiver sends after correct reception of
a byte. If HIDLE is cleared, the reception will be acknowledged by sending a ‘0’ bit on
the SDA line at the ACK clock tick. If HIDLE is set, the reception will not be
acknowledged (a ‘1’ bit is sent). It is used to signal an end-of-data to a slave
transmitter by not generating an ACK on the last byte. As a result, the slave
transmitter must release the SDA line to allow the master to generate the stop event.
If the SHI completes receiving a word and the HRX FIFO is full, the clock will be
Table 5-5 HREQ Function In SHI Slave Modes
HRQE1 HRQE0 HREQ Pin Operation
0 0 High impedance
0 1 Asserted if IOSR is ready to receive a new word
1 0 Asserted if IOSR is ready to transmit a new word
1 1
I
2
C: Asserted if IOSR is ready to transmit or receive
SPI: Asserted if IOSR is ready to transmit and receive