Motorola DSP56012 - Manual (Page 188)

6-10 DSP56012 User’s Manual MOTOROLA
Serial Audio Interface
Serial Audio Interface Programming Model
6.3.1.1 Prescale Modulus select (PM[7:0])—Bits 7–0
The PM[7:0] bits specify the divide ratio of the prescale divider in the SAI baud-rate
generator. A divide ratio between 1 and 256 (PM[7:0] = $00 to $FF) may be selected.
The PM[7:0] bits are cleared during hardware reset and software reset.
Note: The programmer should not use the combination PSR = 1 and
PM[7:0] = 00000000, since it may cause synchronization problems and
improper operation (it is considered an illegal combination).
6.3.1.2 Prescaler Range (PSR)—Bit 8
The Prescaler Range (PSR) bit controls a fixed divide-by-eight prescaler connected in
series with the variable prescale divider. This bit is used to extend the range of the
prescaler for those cases in which a slower clock rate is desired. When PSR is set, the
fixed prescaler is bypassed. When PSR is cleared, the fixed divide-by-eight prescaler
is operational. The PSR bit is cleared during hardware reset and software reset.
6.3.1.3 BRC Reserved Bits—Bits 15–9
Bits 15–9 in the BRC are reserved and unused. They read as 0s and should be written
with 0s for future compatibility.
6.3.2 Receiver Control/Status Register (RCS)
The Receiver Control/Status register (RCS) is a 16-bit read/write control/status
register used to direct the operation of the receive section in the SAI (see Figure 6-4
on page 6-8). The control bits in the RCS determine the serial format of the data
transfers, whereas the status bits of the RCS are used by the DSP programmer to
interrogate the status of the receiver. Receiver-enable and interrupt-enable bits are
also provided in the RCS. When read by the DSP, the RCS appears on the two
low-order bytes of the 24-bit word, and the high-order byte is read as 0s. Hardware
reset and software reset clear all the bits in the RCS. If both R0EN and R1EN bits are
cleared, the receiver section is disabled and it enters the individual reset state. The
individual reset state is entered 1 instruction cycle after bits R0EN and R1EN are
cleared. While in the Stop or individual reset state, the status bits in RCS are also
cleared. Stop or individual reset do not affect the RCS control bits. The programmer
should change the RCS control bits (except for RXIE) only while the receiver section
is in the individual reset state (i.e., disabled), otherwise improper operation may
result. The RCS bits are described in the following paragraphs.
6.3.2.1 RCS Receiver 0 Enable (R0EN)—Bit 0
The read/write Receiver 0 Enable (R0EN) control bit enables the operation of SAI
Receiver 0. When R0EN is set, Receiver 0 is enabled. When R0EN is cleared, Receiver
0 is disabled. If both R0EN and R1EN are cleared, the receiver section is disabled,