Motorola DSP56012 - Manual (Page 159)

Serial Host Interface
Serial Host Interface Programming Model
MOTOROLA DSP56012 User’s Manual 5-11
used in conjunction with the CPOL bit to select the desired clock-to-data relationship.
The CPHA bit, in general, selects the clock edge that captures data and allows it to
change states. It has its greatest impact on the first bit transmitted (MSB) in that it
does or does not allow a clock transition before the data capture edge.
When in Slave mode and CPHA = 0, the SS line must be deasserted and asserted by
the external master between each successive word transfer. SS must remain asserted
between successive bytes within a word. The DSP core should write the next data
word to HTX when HTDE = 1, clearing HTDE. However, the data will be transferred
to the shift register for transmission only when SS is deasserted. HTDE is set when
the data is transferred from HTX to the shift register.
When in Slave mode and CPHA = 1, the SS line may remain asserted between
successive word transfers. The SS must remain asserted between successive bytes
within a word. The DSP core should write the next data word to HTX when
HTDE = 1, clearing HTDE. The HTX data will be transferred to the shift register for
transmission as soon as the shift register is empty. HTDE is set when the data is
transferred from HTX to the shift register.
When in Master mode and CPHA = 0, the DSP core should write the next data word
to HTX when HTDE = 1, clearing HTDE; the data is transferred immediately to the
shift register for transmission. HTDE is set only at the end of the data word
transmission.
Note: The master is responsible for deasserting and asserting the slave device SS line
between word transmissions.
When in Master mode and CPHA = 1, the DSP core should write the next data word
to HTX when HTDE = 1, clearing HTDE. The HTX data will be transferred to the shift
register for transmission as soon as the shift register is empty. HTDE is set when the
data is transferred from HTX to the shift register.
The clock phase and polarity should be identical for both the master and slave SPI
devices. CPHA and CPOL are functional only when the SHI operates in the SPI
mode, and are ignored in the I
2
C mode. The CPHA bit is set and the CPOL bit is
cleared during hardware reset and software reset.
5.4.5.2 HCKR Prescaler Rate Select (HRS)—Bit 2
The HRS bit controls a prescaler in series with the clock generator divider. This bit is
used to extend the range of the divider when slower clock rates are desired. When
HRS is set, the prescaler is bypassed. When HRS is cleared, the fixed divide-by-eight