Figure412 hsr and hcr operation, 5 icr hi flag 1 (hf1)—bit 4, 6 icr hi mode control (hm1 and hm0)—bits 5 and 6 – Motorola DSP56012 User Manual

Page 106: Table43 hi mode bit definition, Icr hi flag 1 (hf1)—bit 4 -26, Icr hi mode control (hm1 and hm0)—bits 5 and 64-26, Figure 4-12, Hsr and hcr operation -26, Table 4-3, Hi mode bit definition -26

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Figure412 hsr and hcr operation, 5 icr hi flag 1 (hf1)—bit 4, 6 icr hi mode control (hm1 and hm0)—bits 5 and 6 | Table43 hi mode bit definition, Icr hi flag 1 (hf1)—bit 4 -26, Icr hi mode control (hm1 and hm0)—bits 5 and 64-26, Figure 4-12, Hsr and hcr operation -26, Table 4-3, Hi mode bit definition -26 | Motorola DSP56012 User Manual | Page 106 / 270 Figure412 hsr and hcr operation, 5 icr hi flag 1 (hf1)—bit 4, 6 icr hi mode control (hm1 and hm0)—bits 5 and 6 | Table43 hi mode bit definition, Icr hi flag 1 (hf1)—bit 4 -26, Icr hi mode control (hm1 and hm0)—bits 5 and 64-26, Figure 4-12, Hsr and hcr operation -26, Table 4-3, Hi mode bit definition -26 | Motorola DSP56012 User Manual | Page 106 / 270
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