2 cvr reserved—bit 6, 3 cvr host command (hc)—bit 7, 6 interrupt status register (isr) – Motorola DSP56012 User Manual

Page 110: 1 isr receive data register full (rxdf)—bit 0, Cvr reserved—bit 6 -30, Cvr host command (hc)—bit 7 -30, Interrupt status register (isr) -30, Isr receive data register full (rxdf)—bit 0 -30

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2 cvr reserved—bit 6, 3 cvr host command (hc)—bit 7, 6 interrupt status register (isr) | 1 isr receive data register full (rxdf)—bit 0, Cvr reserved—bit 6 -30, Cvr host command (hc)—bit 7 -30, Interrupt status register (isr) -30, Isr receive data register full (rxdf)—bit 0 -30 | Motorola DSP56012 User Manual | Page 110 / 270 2 cvr reserved—bit 6, 3 cvr host command (hc)—bit 7, 6 interrupt status register (isr) | 1 isr receive data register full (rxdf)—bit 0, Cvr reserved—bit 6 -30, Cvr host command (hc)—bit 7 -30, Interrupt status register (isr) -30, Isr receive data register full (rxdf)—bit 0 -30 | Motorola DSP56012 User Manual | Page 110 / 270
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