6 shi control/status register (hcsr)—dsp side, 1 hcsr host enable (hen)—bit 0, 1 shi individual reset – Motorola DSP56012 User Manual

Page 161: 2 hcsr i2c/spi selection (hi2c)—bit 1, Shi control/status register (hcsr)—dsp side -13, Hcsr host enable (hen)—bit 0 -13, Shi individual reset -13, Hcsr i

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6 shi control/status register (hcsr)—dsp side, 1 hcsr host enable (hen)—bit 0, 1 shi individual reset | 2 hcsr i2c/spi selection (hi2c)—bit 1, Shi control/status register (hcsr)—dsp side -13, Hcsr host enable (hen)—bit 0 -13, Shi individual reset -13, Hcsr i | Motorola DSP56012 User Manual | Page 161 / 270 6 shi control/status register (hcsr)—dsp side, 1 hcsr host enable (hen)—bit 0, 1 shi individual reset | 2 hcsr i2c/spi selection (hi2c)—bit 1, Shi control/status register (hcsr)—dsp side -13, Hcsr host enable (hen)—bit 0 -13, Shi individual reset -13, Hcsr i | Motorola DSP56012 User Manual | Page 161 / 270
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