Maxim Integrated DS33R11 - Manual (Page 21)

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
21 of 344
Figure 6-2. Block Diagram of T1/E1/J1 Transceiver
TX
LIU
CLOCK
ADAPTER
BACKPLANE
INTERFACE
CIRCUIT
HOST INTERFACE
T1
/E
1
/J
1
NET
W
O
RK
CLOCK
JTAG ESIB
RX
LIU
JI
TTER
ATTEN
U
A
T
O
R
LO
CAL
L
O
O
PBACK
RE
M
O
TE L
O
O
PBACK
FRAM
ER L
O
OPBACK
PA
YL
O
A
D L
O
O
PBACK
MUX
MUX
EXTERNAL ACCESS
TO RECEIVE SIGNALS
EXTERNAL ACCESS
TO TRANSMIT SIGNALS
BACK
PL
ANE
BACKPLANE
CLOCK SYNTH
LIU
FRAMER BACKPLANE
INTERFACE
SYNC
HDLCs
SINGALING
ALARM DET
FRAMER
CRC GEN
SINGALING
ALARM GEN
HDLCs
HDB3 / B8ZS
HDB3 / B8ZS