Maxim Integrated DS33R11 - Manual (Page 50)

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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9.7 Interrupt Information Registers
The interrupt information registers provide an indication of which status registers (SR1 through SR9) are
generating an interrupt. When an interrupt occurs, the host can read TR.IIR1 and TR.IIR2 to quickly identify which
of the nine status registers are causing the interrupt.
9.8 Status Registers
When a particular event or condition has occurred (or is still occurring in the case of conditions), the appropriate bit
in a status register is set to a 1. All of the status registers operate in a latched fashion. This means that if an event
or condition occurs a bit is set to a 1. It remains set until the user reads that bit. An event bit is cleared when it is
read and it is not set again until the event has occurred again. Condition bits such as RBL, RLOS, etc., remain set
if the alarm is still present.
The user always proceeds a read of any of the status registers with a write. The byte written to the register informs
the device which bits the user wishes to read and have cleared. The user writes a byte to one of these registers,
with a 1 in the bit positions the user wishes to read and a 0 in the bit positions the user does not wish to obtain the
latest information on. When a 1 is written to a bit location, the read register is updated with the latest information.
When a 0 is written to a bit position, the read register is not updated and the previous value is held. A write to the
status registers is immediately followed by a read of the same register. This write-read scheme allows an external
microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register.
This operation is key in controlling the device with higher order languages.
Status register bits are divided into two groups, condition bits and event bits. Condition bits are typically network
conditions such as loss-of-sync or all-ones detect. Event bits are typically markers such as the one-second timer,
elastic store slip, etc. Each status register bit is labeled as a condition or event bit. Some of the status registers
have bits for both the detection of a condition and the clearance of the condition. For example, TR.SR2 has a bit
that is set when the device goes into a loss-of-sync state (TR.SR2.0, a condition bit) and a bit that is set
(TR.SR2.4, an event bit) when the loss-of-sync condition clears (goes in sync). Some of the status register bits
(condition bits) do not have a separate bit for the “condition clear” event but rather the status bit can produce
interrupts on both edges, setting and clearing. These bits are marked as double interrupt bits. An interrupt is
produced when the condition occurs and when it clears.
9.9 Information Registers
Information registers operate the same as status registers except they cannot cause interrupts. They are all
latched except for TR.INFO7 and some of the bits in TR.INFO5 and TR.INFO6. TR.INFO7 register is a read-only
register. It reports the status of the E1 synchronizer in real time. TR.INFO7 and some of the bits in TR.INFO6 and
TR.INFO5 are not latched and it is not necessary to precede a read of these bits with a write.
9.10 Serial Interface
The Serial (WAN) interface is intended to be connected to the integrated T1/E1/J1 Transceiver. However, the
interface supports time-division multiplexed, serial data input and output up to 52 Mbit/s. The Serial interface
receives and transmits encapsulated Ethernet packets. The Serial Interface block consists of the physical serial
port and HDLC / X.86 engine. The physical interface consists of a Transmit Data, Transmit Clock, Transmit Enable,
Receive Data, Receive Clock, and Receive Enable. The WAN serial port can operate with a gapped clock, and can
be connected to a framer, electrical LIU, optical transceiver, or T/E-Carrier transceiver for transmission to the
WAN.