Maxim Integrated DS33R11 - Manual (Page 215)

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
215 of 344
Register Name: TR.SR1
Register Description: Status Register 1
Register Address: 16h
Bit
# 7 6 5 4 3 2 1 0
Name ILUT TIMER RSCOS JALT LRCL TCLE TOCD LOLITC
Default 0 0 0 0 0 0 0 0
Bit 7: Input Level Under Threshold (ILUT). This bit is set whenever the input level at RTIP and RRING falls
below the threshold set by the value in TR.CCR4.4 through TR.CCR4.7. The level must remain below the
programmed threshold for approximately 50ms for this bit to be set. This is a double interrupt bit (Section
9.7 ).
Bit 6: Timer Event (TIMER). Follows the error-counter update interval as determined by the ECUS bit in the error-
counter configuration register (TR.ERCNT).
T1: set on increments of 1 second or 42ms based on RCLKO
E1: set on increments of 1 second or 62.5ms based on RCLKO
Bit 5: Receive Signaling Change-of-State Event (RSCOS). Set when any channel selected by the receive
signaling change-of-state interrupt-enable registers (TR.RSCSE1 through TR.RSCSE4) changes signaling state.
Bit 4: Jitter Attenuator Limit Trip Event (JALT). Set when the jitter attenuator FIFO reaches to within 4 bits of its
useful limit. This bit is cleared when read. Useful for debugging jitter attenuation operation.
Bit 3: Line Interface Receive Carrier-Loss Condition (LRCL). Set when the carrier signal is lost. This is a
double interrupt bit (Section
9.7 ).
Bit 2: Transmit Current-Limit Exceeded Condition (TCLE). Set when the 50mA (RMS) current limiter is
activated, whether the current limiter is enabled or not. This is a double interrupt bit (Section
9.7 ).
Bit 1: Transmit Open-Circuit Detect Condition (TOCD). Set when the device detects that the TTIP and TRING
outputs are open-circuited. This is a double interrupt bit (Section
9.7 ).
Bit 0: Loss of Line-Interface Transmit-Clock Condition (LOLITC). Set when TDCLKI has not transitioned for
one channel time. This is a double interrupt bit (Section
9.7 ).