Kane Industries C6713CPU - Manual (Page 12)

H ARDWARE R EFERENCE G UIDE
MICRO - LINE
®
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 12
2.2 Connectors
2.2.1 micro-line
®
Connectors
The micro-line ® connectors are the main I/O connectors of the C6713CPU. They provide access to
all signals that are needed for a wide range of I/O connectivity. The signals on the micro-line ®
connectors can be grouped into the following categories:
• power supply
• DSP- and board specific interfaces, such as timers and serial ports
• FPGA specific signals (their function depend on the respective FPGA design)
Historically (without FPGA) the micro-line
® connectors carried the following signals:
• power supply
• DSP- and board specific interfaces, such as timers and serial ports
• the micro-line ® peripheral interface which allowed straightforward access to peripherals
Today, with FPGA technology onboard, many of the micro-line
® I/O signals can be individually
hardware-configured for nearly any application. This is possible by building an individual,
application-specific FPGA design which exactly covers the application's requirements.
Nevertheless, the micro-line
® standard peripheral interface is still available as a board support
package, the micro-line busmaster BSP ® . It is the default configuration when the C6713CPU board
is shipped from ORSYS. The pinning of the micro-line ® connectors (without any particular FPGA
design loaded) is described in chapter 6. The pinning and functionality of the micro-line ® busmaster
BSP is described in [21].
2.2.2 JTAG Connector
The JTAG connector is used during development of application software or FPGA designs. It
contains two separate JTAG interfaces, one for the DSP and one for the FPGA.
The DSP JTAG interface is used for debugging and application software download during
development, together with Texas Instruments Code Composer Studio and an XDS510 (or similar)
emulator. After the software development is finalized, the user application software can be
downloaded from the development PC to the C6713CPU's flash memory via RS232 for permanent
storage. This is managed by the Flash File System which is permanently installed on the
C6713CPU.
The FPGA JTAG interface can be used to quickly download and test FPGA designs during
development without permanent storage on the C6713CPU. After the FPGA development is
finalized, the FPGA design can be downloaded from the development PC via RS232 to the
C6713CPU's flash memory for permanent storage. This is managed by the Flash File System
which is permanently installed on the C6713CPU.
In order to connect a standard DSP JTAG emulator or a standard FPGA download cable to the
C6713CPU, a JTAG adapter is used, which is included in C6713CPU development kits. The JTAG
adapter is described in chapter 6.4.
2.3 Interfaces and Hardware Components
2.3.1 FPGA
The default FPGA design for the C6713CPU can be used for standard micro-line
® bus compatible
applications. Alternatively the FPGA can be individually programmed by the user. This is possible
by using an optional FPGA development package from ORSYS together with standard FPGA
development tools from Xilinx. FPGA technology allows flexible internal logic and individual I/O